Interrupt Control Unit
7-7
7.1.5
Interrupt Acknowledge
Interrupts can be acknowledged in two different ways—the internal interrupt controller can
provide the interrupt type or an external interrupt controller can provide the interrupt type.
The processor requires the interrupt type as an index into the interrupt vector table.
When the internal interrupt controller is supplying the interrupt type, no bus cycles are
generated. The only external indication that an interrupt is being serviced is the processor
reading the interrupt vector table.
When an external interrupt controller is supplying the interrupt type, the processor
generates two interrupt acknowledge bus cycles (see Figure 7-1). The interrupt type is
written to the AD7–AD0 lines by the external interrupt controller during the second bus cycle.
Interrupt acknowledge bus cycles have the following characteristics:
n
The two interrupt acknowledge cycles are internally locked. (There is no LOCK pin on
the Am186EM and Am188EM microcontrollers.)
n
Two idle states are always inserted between the two cycles.
n
Wait states are inserted if READY is not returned to the processor.
Figure 7-1
External Interrupt Acknowledge Bus Cycles
Notes:
1. ALE is active for each INTA cycle.
2. RD is inactive.
T1
T2
T3
T4
T1
T2
T3
T4
S0–S2
INTA
Internal lock
Ti
Ti
Interrupt
Acknowledge
Interrupt
Acknowledge
AD7–AD0
Interrupt
Type
Summary of Contents for AM186EM
Page 1: ...Am186 EM and Am188 EM Microcontrollers User s Manual...
Page 4: ...iv...
Page 12: ...Table of Contents xii...
Page 62: ...Peripheral Control Block 4 10...
Page 76: ...Chip Select Unit 5 14...
Page 122: ...Timer Control Unit 8 8...
Page 136: ...DMA Controller 9 14...
Page 144: ...Asynchronous Serial Port 10 8...
Page 158: ...Programmable I O Pins 12 6...
Page 186: ...Index I 12...