Altera Stratix GX, User Manual

Page: 277 / 318

Altera Corporation 9–51
January 2005 Stratix GX Transceiver User Guide
Reset Control & Power Down
end
else
begin
if(sync_reset)
begin
rxanalogreset <= 1'b1;
rxdigitalreset_rx_cruclk<= 1'b1;
waitstate_timer <=
WAITSTATE_TIMER_VALUE;
end
else
begin
rxanalogreset <= 1'b0;
if (rx_freqlocked)
begin
if(waitstate_timer == 0)
begin
waitstate_timer
<= waitstate_timer;
if(receive_digitalreset)
rxdigitalreset_rx_cruclk <= 1'b1;
else
rxdigitalreset_rx_cruclk <= 1'b0;
end
else
begin
waitstate_timer
<= waitstate_timer - 1'b1;
rxdigitalreset_rx_cruclk <= 1'b1;
end
end
else
begin
rxdigitalreset_rx_cruclk <= 1'b1;
waitstate_timer <=
WAITSTATE_TIMER_VALUE;
end
end
end
/*synchronizing the rxdigitalreset to recovered clock domain
If rxdigitalreset is only used for Receive GXB, then this
synchronization is not needed because internally the
rxdigitalreset is only synchronized to recovered clock
(rx_clkout). In the above description of the module, a designer
likes to operate on the system clock or PLD clock domain where one
would like to have a FIFO with rx_clkout domain being write clock
and may have pld clock domain(Generic name, can be any clock name)
as read clock. pld clock is optional. To reset the rx_clkout
domain logic in PLD fabric following reset is useful*/