Altera Stratix GX, User Manual

Page: 265 / 318

Altera Corporation 9–39
January 2005 Stratix GX Transceiver User Guide
Reset Control & Power Down
/*synchronizing the rxdigitalreset to recovered clock domain
If rxdigitalreset is used for Receive GXB, then this
synchronization is needed because
internally the rxdigitalreset is synchronized to recovered clock
(rx_clkout).To reset the rx_coreclk domain logic in
PLD fabric following reset is useful
*/
always @(posedge rx_coreclk or posedge async_reset)
if(async_reset)
begin
rxdigitalreset_rx_coreclk_Q <= 1'b1;
rxdigitalreset <= 1'b1;
end
else
begin
if(receive_digitalreset)
begin
rxdigitalreset_rx_coreclk_Q <= 1'b1;
rxdigitalreset <= 1'b1;
end
else
begin
rxdigitalreset_rx_coreclk_Q <=
rxdigitalreset_inclk;
rxdigitalreset <=
rxdigitalreset_rx_coreclk_Q;
end
end
endmodule
Design Example 2
This design example shows a receive-only configuration where
inclk
is
the transmit PLL input reference clock, the output of transmit PLL trains
receive CRU, and
rx_clkout
is the receive parallel interface clock.
This design example has the following constraints:
■
If your design requirements are different from the examples, use the
flow charts and waveforms for each configuration as design
guidelines.
■
The design example requires a reset controller that generates a
sync_reset
(synchronous reset) for the entire system.
■
The design example has an
async_reset
(a power down in GXB
terms) and digital resets for transmit and receive. All user input
digital resets must be at least four cycles long.
■
This design example does not cover all the digital reset scenarios in
a system that resets the digital logic of the GXB.