Altera Stratix GX, User Manual

Page: 251 / 318

Altera Corporation 9–25
January 2005 Stratix GX Transceiver User Guide
Reset Control & Power Down
STROBE_TXPLL_LOCKED: if (sync_reset) //Synchronous Reset
can be asserted in IDLE state (After reset seq has finished)
begin
txdigitalreset <= 1'b1;
pll_areset <= 1'b1;
state <= STROBE_TXPLL_LOCKED;
end
//Wait untill the TXPLL is locked to inclk and TX PLL has a
stable output clock which is also fed to RX CRU
else if (pll_locked)
begin
state <= STABLE_TX_PLL;
txdigitalreset<= 1'b0;
pll_areset <= 1'b0;
end
else
begin
state <= STROBE_TXPLL_LOCKED;
txdigitalreset <= 1'b1;
pll_areset <= 1'b0;
end
STABLE_TX_PLL: if (sync_reset) //Synchronous Reset can
be asserted in IDLE state (After reset seq has finished)
begin
txdigitalreset <= 1'b1;
pll_areset <= 1'b1;
state <= STROBE_TXPLL_LOCKED;
end
else
state <= IDLE;
default: state = IDLE;
endcase
end
//Receive Reset Sequence
always @(posedge rx_cruclk or posedge pll_areset)
if(pll_areset)
begin
rxanalogreset <= 1'b1;
rxdigitalreset_rx_cruclk <= 1'b1;
waitstate_timer <=
WAITSTATE_TIMER_VALUE;
end
else
begin
if(sync_reset)
begin
rxanalogreset <= 1'b1;
rxdigitalreset_rx_cruclk<= 1'b1;
waitstate_timer <=
WAITSTATE_TIMER_VALUE;
end
else
begin
rxanalogreset <= 1'b0;
if (rx_freqlocked)
begin
if(waitstate_timer == 0)