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Altera Stratix GX, User Manual

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Altera Stratix GX User Manual Download Page 131

Altera Corporation 

  

5–19

January 2005

Stratix GX Transceiver User Guide

XAUI Mode

receive a clock supply. In this case, there must be no frequency difference 
between the 

tx_coreclk

 and the transmitter PLL clock. The transmitter 

Phase Compensation FIFO module can only account for phase 
differences.

If the 

tx_coreclk

 is not selected as an optional input transmitter port, 

tx_coreclk

 is fed by 

coreclk_out

. This connection occurs using the 

logic array routing. As such, the software defaults to using an FPGA 
global clock, regional clock, or fast regional clock resource. 

The transmitter phase compensation FIFO module is always used and 
cannot be bypassed. The input to this FIFO module is the data from the 
FPGA logic array. If they are used, the 

tx_ctrlenable

 and 

tx_forcedisparity

 signals are also passed through the FIFO module 

to ensure that they are synchronized with the data when they feed to the 
subsequent module.

Byte Serializer

The byte serializer in the transmitter block takes a 16-bit input from the 
FPGA logic array and serializes it to 8 bits. It transmits from the least 
significant byte to the most significant byte. The transmitter digital reset 
must always be used to reset the FIFO module pointers whenever an 
unknown state is encountered, such as when the transmitter PLL loses 
lock. Refer to the chapter 

Reset Control & Power Down

 for further details 

on the reset sequence.

Figure 5–16

 demonstrates input and output signals of the byte serializer 

when serializing a 20-bit input to 10 bits. The 

tx_in[]

 signal is the input 

that has already passed from the FPGA logic array through the 
transmitter phase compensation FIFO module.

Figure 5–16. Transmitter Byte Serializer in 16- to 8-Bit Mode

The LSB is transmitted before the MSB in the transmitter byte serializer. 

Figure 5–16

 shows the order of data transmitted. For the input of D1, the 

output is D1LSB and then D1MSB.

xxxxxxxx

xxxxxxxx

01101111

0001010001101111

datain[15:0]

dataout[7:0]

1100011011110001

1010101010110011

00010100

11110001

11000110

D1

D2

D3

D1 LSB

D1 MSB

D2 LSB

D2 MSB

Summary of Contents for Stratix GX

Page 1: ...101 Innovation Drive San Jose CA 95134 408 544 7000 http www altera com Stratix GX Transceiver User Guide UG STXGX 3 0 P25 10021 02 ...

Page 2: ...ending applications maskwork rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the ap plication or use of any information product or service d...

Page 3: ...ption Introduction 2 1 Transmitter Analog 2 2 Transmitter Buffer 2 2 Transmitter PLL 2 5 Serializer Parallel to Serial Converter 2 8 Receiver Analog 2 9 Receiver Input Buffer 2 9 Receiver PLL 2 12 Clock Recovery Unit 2 16 Deserializer Serial to Parallel Converter 2 19 MegaWizard Analog Features 2 20 MegaWizard Analog Feature Considerations 2 20 Chapter 3 Basic Mode Introduction 3 1 Basic Mode Rece...

Page 4: ... Mode Channel Clocking 4 12 SONET Mode Inter Transceiver Block Clocking 4 17 SONET Mode MegaWizard Plug In Manager 4 23 SONET Mode MegaWizard Considerations 4 23 SONET Mode altgxb MegaWizard Options 4 23 Chapter 5 XAUI Mode Introduction 5 1 XAUI Mode Receiver Architecture 5 5 Word Aligner 5 6 Channel Aligner 5 9 Rate Matcher 5 11 8B 10B Decoder 5 11 PCS XGMII Code Conversion 5 15 Byte Deserializer...

Page 5: ...n Waveform Hardware Verification Results 6 44 Chapter 7 Loopback Modes Introduction 7 1 Serial Loopback 7 1 Parallel Loopback 7 2 Reverse Serial Loopback 7 3 Chapter 8 Stratix GX Built In Self Test BIST Introduction 8 1 Pattern Generator 8 2 PRBS Mode Generator 8 2 Incremental Mode Generator 8 3 High Frequency Mode Generator 8 3 Low Frequency Mode Generator 8 4 Mix Frequency Mode Generator 8 5 Pat...

Page 6: ... Receiver Transmitter Reset 9 4 Receiver Reset 9 32 Transmitter Reset 9 52 Power Down 9 57 Appendix A Data Control Codes 8B 10B Code A 1 Code Notation A 1 Disparity Calculation A 1 Supported Codes A 3 Appendix B Ports Parameters Input Ports B 1 Output Ports B 5 Parameter Descriptions B 9 Appendix C REFCLKB Pin Constraints Known Issues C 1 Quartus II Software Messages C 3 Recommendations C 5 ...

Page 7: ...sult the sources shown below Information Type USA Canada All Other Locations Technical support www altera com mysupport www altera com mysupport 800 800 EPLD 3753 7 00 a m to 5 00 p m Pacific Time 1 408 544 8767 7 00 a m to 5 00 p m GMT 8 00 Pacific Time Product literature www altera com www altera com Altera literature services literature altera com literature altera com Non technical customer se...

Page 8: ...board keys and menu names are shown with initial capital letters Examples Delete key the Options menu Subheading Title References to sections of a document and titles of on line help topics are shown in quotation marks Example Typographic Conventions Courier type Signal and port names are shown in lowercase Courier type Examples data1 tdi input Active low signals are denoted by suffix n e g resetn...

Page 9: ...f embedded functions and does the following Supports frequencies from 500 megabits per second Mbps to 3 1875 Gbps Integrates serializer deserializer SERDES clock data recovery CDR word aligner channel aligner rate matcher 8B 10B encoder decoder byte serializer deserializer and phase compensation first in first out FIFO modules Supports flexible reference clock generation capabilities including a d...

Page 10: ... I O buffers support the 1 5 V PCML I O standard and contain features that improve system signal integrity These features include programmable pre emphasis which helps compensate for high frequency losses and a variety of programmable VOD settings that support noise margin tuning Receiver Differential I O Buffers The gigabit transceiver block differential I O buffers support the 1 5 V PCML I O sta...

Page 11: ...ned with the incoming data thereby eliminating any clock to data skew This recovered clock then clocks the data through the rest of the gigabit transceiver block Serializer Deserializer SERDES The transmitter serializer converts the incoming lower speed parallel signal to a high speed serial signal on the transmit side The SERDES supports a variety of conversion factors ensuring implementation fle...

Page 12: ...oding is the backbone of many transceiver protocols and it is often used in proprietary implementations The gigabit transceiver block has dedicated circuitry to perform 8B 10B encoding in the transmitter and decoding in the receiver This coding technique ensures sufficient data transitions and a DC balanced stream in the data signal for successful data recovery at the receiver Word Aligner The wor...

Page 13: ... frequency differences between the recovered clock and the FPGA logic array clock by inserting or deleting removable characters from the data stream as defined by the transmission protocol without compromising transmitted data If the functional mode is XAUI the rate matcher is based on the 10 Gigabit Ethernet protocol If the functional mode is GigE the rate matcher is based on the Gigabit Ethernet...

Page 14: ...der decoder channel aligner and the rate matcher features are not available Refer to the SONET Mode chapter for more details on the configurability of this mode Figure 1 3 shows a block diagram of a duplex channel configured in SONET mode Deserializer Serializer Word Aligner 8B 10B Decoder Channel Aligner Byte Deserializer 8B 10B Encoder Phase Compensation FIFO Buffer Reference Clock Reference Clo...

Page 15: ...eskew rate matching XGXS to XGMII and XGMII to XGXS code group conversion Refer to the XAUI Mode chapter for more details on the configurability of this mode Figure 1 4 shows a block diagram of a duplex channel configured in XAUI mode Deserializer Serializer Word Aligner 8B 10B Decoder Channel Aligner Byte Deserializer 8B 10B Encoder Phase Compensation FIFO Buffer Reference Clock Reference Clock B...

Page 16: ...on about this mode The rate matcher and word aligner each have a dedicated state machine governing their functions These state machines are active only in GigE mode Figure 1 5 shows a block diagram of a duplex channel configured in GigE mode Deserializer Serializer Word Aligner 8B 10B Decoder Channel Aligner Byte Deserializer 8B 10B Encoder Phase Compensation FIFO Buffer Reference Clock Reference ...

Page 17: ... An embedded PRBS pattern generator provides a bitstream pattern that you can use to test the device and board connections The PRBS pattern generator works with a PRBS receiver to implement a full self test path Additionally serial and parallel loopback paths let you test the FPGA logic without monitoring external signals The reverse loopback path enables external system testing with minimal devic...

Page 18: ...1 10 Altera Corporation Stratix GX Transceiver User Guide January 2005 Modes of Operation ...

Page 19: ...ses and inter symbol interference These features are useful in lossy transmission lines Transceivers also support flexible reference clock generation capabilities including a dedicated transmitter phase locked loop PLL and four receiver PLLs per transceiver block The clock recovery unit CRU is the main part of each receive analog section it recovers the clock from the serial data stream see Figure...

Page 20: ...e capable of driving 40 inches of FR4 trace across two connectors In addition the buffer contains programmable output voltage programmable pre emphasis circuitry and internal termination circuitry Deserializer Serializer Word Aligner 8B 10B Decoder Channel Aligner Byte Deserializer 8B 10B Encoder Phase Compensation FIFO Buffer Reference Clock Reference Clock Byte Serializer Phase Compensation FIFO...

Page 21: ...l from a range of 400 to 1 600 mV as shown in Table 2 1 Figure 2 3 VOD Differential Signal Level Table 2 1 shows the differential output voltage VOD setting per current level for each of the on chip transmitter programmable termination values Single Ended Waveform Differential Waveform VOD Differential 2 x VOD single ended Positive Channel p VOH Negative Channel n VOL Ground VOD VOD VOD p n 0 V VC...

Page 22: ...y Refer to the section MegaWizard Analog Features on page 2 20 for further details Programmable Pre Emphasis The programmable pre emphasis module in each transmit buffer boosts the high frequencies in the transmit data signal which may be attenuated in the transmission media This maximizes the data eye opening at the far end receiver Pre emphasis is particularly useful in lossy transmission medium...

Page 23: ...phasis of each channel to be configured independently For further details refer to MegaWizard Analog Features on page 2 20 Avoid pre emphasis and VOD settings that yield a value greater than 1 600 mV Settings beyond this value do not damage the buffer but they prevent accurate device operation Verify that the combination of VOD and pre emphasis settings do not exceed the 1 600 mV limit Programmabl...

Page 24: ...with a 622 MHz reference clock In this scenario the reference clock must be assigned to the REFCLKB port where the 622 MHz reference clock is divided by 2 yielding a 311 MHz clock at the PFD This 311 MHz reference clock is then multiplied by a factor of 8 to achieve the 2 488 MHz clock at the VCO 2 Inter Quad Routing IQ1 Inter Quad Routing IQ0 Global Clocks I O Bus General Routing Dedicated Local ...

Page 25: ...is achieved in the same manner by pre dividing the reference clock by 2 and then multiplying the resultant frequency by 10 which yields a multiplication factor of 5 Table 2 3 lists the possible multiplication values as a function of the source to the transmitter PLL Table 2 3 assumes that the reference clock is directly fed from the source listed and does not factor any pre clock synthesis that is...

Page 26: ...ystems Serializer Parallel to Serial Converter The serializer converts parallel data to serial data at the transmitter output buffer The serializer can support 8 or 10 bit words when used with the transmitter multiplexer The 8 bit serializer drives the serial data to the output buffer as shown in Figure 2 5 The serializer can drive the serial bit stream at a data rate range of 500 Mbps to 3 1875 G...

Page 27: ...mination and internal equalization Figure 2 8 shows the structure of the input buffer The input buffer has programmable equalization that you can apply to increase the signal integrity of the transmission line The internal termination in the receiver buffer can support AC and DC coupling with programmable differential termination settings of 100 120 or 150 Ω Parallel Clock Serial Clock Parallel Da...

Page 28: ...s receiver only configurations in Stratix GX devices However if you use the Quartus II software to remove the transmitter PLL in a receiver only configuration you will see an incorrect value or unpredictable behavior with the receiver input pin termination If the rx_cruclk signal is globally routed the Quartus II software handles this automatically If the rx_cruclk signal is not globally routed or...

Page 29: ...ability with the Stratix GX transmitter Equalizer Mode Stratix GX transceivers offer an equalization circuit in each receiver channel to increase noise margins and help reduce the effects of high frequency losses The programmable equalizer compensates for inter symbol interference ISI and high frequency losses that distort the signal and reduce the noise margin of the transmission medium by equali...

Page 30: ...regenerating another programming file On the other hand if you select the dynamic adjustment in the altgxb MegaWizard Plug In the equalization setting can be configured dynamically by the device during user mode This configuration is accomplished by asserting encoded values on the rx_equalizerctrl signal which is instantiated in the altgxb module when this option is selected This feature lets you ...

Page 31: ...vider on the dedicated local REFCLKB path This divides the reference clock frequency by a factor of 2 and then the m factor compensates the frequency difference For example given a data rate of 2 488 Mbps with a reference clock of 622 MHz the reference clock must be assigned to the REFCLKB port RX_CRUCLK CP LF Up Down VCO m RX_IN High Speed RCVD_CLK Low Speed RCVD_CLK Global Clks I O Bus Gen Routi...

Page 32: ...equency by 8 which yields a multiplication factor of 4 A multiplication factor of 5 is achieved in the same manner by pre dividing the reference clock by 2 and then multiplying the resulting frequency by 10 which yields a multiplication factor of 5 The MegaWizard Plug In altgxb option enables the transmitter PLL in receiver mode There is also an option to train the receiver CRU with the output of ...

Page 33: ...utput of the PPM frequency threshold detector is one of the variables that asserts the rx_freqlocked signal Refer to Clock Recovery Unit on page 2 16 for more detail regarding the rx_freqlocked signal Receiver Bandwidth Type The Stratix GX receiver PLL in the CRU offers a programmable bandwidth setting The bandwidth of a data recovery PLL is the measure of its ability to track the input data and j...

Page 34: ...n length is exceeded run length violation detection circuit Lock to Reference Mode Lock to Data Mode The Stratix GX device offers both automatic and manual locking options as described in the following sections Automatic Lock Mode By default the CRU initially locks to the CRU reference clock RX_CRUCLK lock to reference mode until conditions warrant the switchover to the incoming data lock to data ...

Page 35: ... lock to data mode the rx_freqlocked signal is asserted and the rx_locked signal looses its significance The rx_locked signal signifies that the CRU has locked to the reference clock When the CRU is in lock to data mode the rx_locked signal behavior is not predictable In automatic lock mode CRU is forced out of lock to data mode if the CRU PLL is not within the recommended PPM frequency threshold ...

Page 36: ..._locktorefclk goes high the rx_freqlocked signal is ignored and does not toggle The rx_freqlocked signal always goes high if lock to data mode is asserted If you want to transition from lock to data mode to automatic mode the transition should be followed by rx_analogreset to send the rx_freqlocked signal low The CRU does not often transition from manual mode to automatic mode during system operat...

Page 37: ...d to the recovered clock of the CRU The deserializer drives the parallel data to the pattern detector and word aligner as shown in Figure 2 11 The data rate of the deserializer output bus is the input data rate divided by the width of the output data bus For example for a 10 bit bus and a serial input data rate of 2 5 Gbps the parallel data rate is 2500 10 or 250 MHz The first bit into the deseria...

Page 38: ...recommends using the MegaWizard Plug In Manager to instantiate your altgxb megafunction reducing the likelihood of invalid settings MegaWizard Analog Feature Considerations Each altgxb MegaWizard Plug In uses one or more transceiver blocks based on the number of channels you select There are four channels per transceiver block If a MegaWizard Plug In Manager instantiation uses fewer than four chan...

Page 39: ...s An additional input receiver reference clock rx_cruclk is available when this option is turned off The first option that is enabled is needed for non encoded 16 bit modes with a line rate of 2 600 Mbps or greater For more details regarding this feature refer to Clock Synthesis on page 2 6 3 Selectable High and Low High bandwidth supports faster lock times It also tracks higher frequency jitter b...

Page 40: ...y 2005 MegaWizard Analog Features Figure 2 14 MegaWizard Plug In Manager ALTGXB Page 2 of 7 General 2 Notes 1 2 Notes to Figure 2 14 1 For information refer to the Loopback Modes chapter 2 For more information refer to the Stratix GX Built In Self Test BIST chapter ...

Page 41: ...r 1 Note 1 Note to Figure 2 15 1 Enable run length violation circuit If enabled the optional output pin rx_rlv pin is available and pulses high when the specified run length is violated In 8 bit or 16 bit mode set the run length threshold from 4 to 124 in steps of 4 In 10 bit and 20 bit mode or if using 8b10b set the run length threshold from 5 to 160 in steps of 5 ...

Page 42: ...qualization via the optional rx_equalizerctrl input port If this control signal is not used you can set equalization in the MegaWizard Plug In Manager via the Select the equalizer control setting The valid values are 0 through 4 with 0 being off and 4 being the largest gain setting 3 Available settings are High Medium and Low High bandwidth allows for faster lock times and tracks higher frequency ...

Page 43: ... rx_locktodata are asserted then rx_locktodata takes precedence 2 Optional input signal that forces the CRU to lock to the incoming data If both rx_locktorefclk and rx_locktodata are asserted rx_locktodata takes precedence 3 Optional output signal that indicates when the CRU is locked to the incoming data stream The lock indication is based on the following conditions a The CRU PLL is within the p...

Page 44: ...g In Manager via the Select the VOD control setting option The valid values are based on your transmitter termination value and range from 400 to 1 600 mV 2 The Use Preemphasis control signal option enables dynamic pre emphasis control using the optional tx_preemphasisctrl input port If this control signal is not used set the pre emphasis in the MegaWizard Plug In Manager using the Select the pree...

Page 45: ...Altera Corporation 2 27 January 2005 Stratix GX Transceiver User Guide Stratix GX Analog Description Figure 2 19 MegaWizard Plug In Manager ALTGXB Page 7of 7 Summary ...

Page 46: ...2 28 Altera Corporation Stratix GX Transceiver User Guide January 2005 MegaWizard Analog Features ...

Page 47: ...erially over a medium can use the basic mode offered by Stratix GX devices The basic mode includes SERDES and parallel interconnect functionality In this mode the transceiver performs serialization and de serialization with an optional 8B 10B coding scheme Basic mode is not aware of the system level protocol wrapped on top of it Basic mode enables a subset of the transceiver blocks for customizabl...

Page 48: ...he need to factor in receiver skew margins between the clock and data However with this clocking methodology the word boundary of the re timed data can be altered Stratix GX devices offer an embedded Deserializer Serializer Word Aligner 8B 10B Decoder Channel Aligner Byte Deserializer 8B 10B Encoder Phase Compensation FIFO Buffer Reference Clock Reference Clock Byte Serializer Phase Compensation F...

Page 49: ...ignal is not used the word aligner does not alter the data Figure 3 3 shows the various components of the word aligner in basic mode The functionality is described in the following sections Figure 3 3 Components in the Stratix GX Word Aligner Pattern Detector Module The pattern detector matches a predefined comma to the current byte boundary If the comma is found the optional rx_patterndetect sign...

Page 50: ...the data and its complement in the current word boundary Both positive and negative disparities are also checked in this mode The 7 bit pattern mode is useful because it can mask out the three most significant bits of the data This lets the pattern detector recognize multiple commas For example in the 8b 10b encoded data a K28 5 b 0011111010 K28 1 b 0011111001 and K28 7 b 0011111000 shares seven c...

Page 51: ...gn uses an encoding scheme such as 8B 10B to guarantee that the K28 5 code group is a unique pattern in the data stream the rx_enacdet is held high In situations where the comma exists between word boundaries rx_enacdet must be controlled to avoid false word alignment For example suppose that you use 8B 10B encoding and specify a D19 1 b 110010 1001 character as the comma In this case a false word...

Page 52: ...se the bit orientation of the Stratix GX device is LSB to MSB it follows from the waveform that the comma exists across time n 2 and n 3 In this condition the rx_patterndetect signal remains low because the comma does not exist on the current word boundary but the rx_syncstatus signal is asserted for one clock cycle to signify a resynchronization condition This means that the comma has been detect...

Page 53: ...nt mode for an A1A2 pattern Figure 3 6 Example of How the Word Aligner Signals Interact in SONET A1A2 Manual Alignment Mode In Figure 3 6 the rx_enacdet signal is toggled high at time n at which point the aligner locks to the boundary of the next present comma The A1 comma also appears on the rx_word_align_out port during this period At time n 1 the A2 comma appears on the rx_word_align_out port B...

Page 54: ...is useful if the comma changes dynamically when the Stratix GX device is in user mode Because the controller is implemented in the logic array a custom controller can be built to dynamically change the comma without needing to reprogram the Stratix GX device Figure 3 7 shows an example of how the word aligner signals interact in the manual bitslip alignment mode For this example 8 b00111100 is spe...

Page 55: ...tect and code error are pipelined with the data in the Stratix GX receiver block and are edge aligned with the data Figure 3 8 diagrams the 10 bit to 8 bit conversion Table 3 2 Word Alignment Support for Basic Mode Word Alignment Mode Effective Mode Control Signals Status Signals Manual 10 bit alignment Mode Alignment to detected pattern when allowed by the rx_enacdet signal rx_enacdet rx_syncstat...

Page 56: ...valid data or control codes Code Error Detect The rx_errdetect signal indicates when the code that is received contains an error This port is optional and if not in use there is no way to determine whether a code that is received is valid The rx_errdetect signal goes high if a code received is an invalid code or if it contains a disparity error If a code is received that is not part of the valid D...

Page 57: ... transitions high rx_errdetect also transitions high Figure 3 9 shows a case where the disparity is violated A K28 5 code has an 8 bit value of 8 hbc and a 10 bit value jhgfiedcba The 10 bit value is 10 b0011111010 10 h17c for RD or 10 b1100000101 10 h283 for RD Assume that the running disparity at time n 1 is negative so the expected code at time n is taken from the RD column Because a K28 5 does...

Page 58: ...e 3 10 shows an example waveform demonstrating the receipt of a K28 5 code BC ctrl The rx_ctrldetect 1 b1 is aligned with 8 hbc indicating that it is a control code Figure 3 10 Control Code Detection clock rx_out 7 0 rx_disperr BC BC BC BC BC BC rx_ctrldetect BC Expected RD code rx_in 17C 283 17C 283 283 283 17C 17C RD RD RD RD RD RD RD RD RD code received RD RD RD RD RD RD RD RD n n 1 n 2 n 3 n 4...

Page 59: ...yncstatus and rx_a1a2sizeout 8 bits of data and up to five control signals rx_patterndetect rx_syncstatus rx_disperr rx_ctrldetect and rx_errdetect 10 bits of data and up to two control signals rx_patterndetect and rx_syncstatus The byte deserializer outputs up to 26 bits depending on the number of bits that was passed to it When the input includes data and control signals the data and the control...

Page 60: ...LSB You must implement logic for byte position alignment if necessary once data enters the logic array as seen in Figure 3 13 In this example the byte position selection logic determines the proper byte position based on the pattern detect signal xxxxxxxxxx 1010100000 1100011000 xxxxxxxxxxxxxxxxxxxx inclk data_in 9 0 data_out 19 0 1111000111 1010101010 1100110011 patterndetect 0 patterndetect 1 A ...

Page 61: ...cked by the recovered clock from the CRU This clock is half the original rate if the byte deserializer is used The read clock is clocked by RX_CORECLK You can select RX_CORECLK as an optional receiver input port and it can also accept a clock supply The clock that feeds the RX_CORECLK must be derived from the RX_CLKOUT of its associated receiver channel The receiver phase compensation FIFO buffer ...

Page 62: ... diagram of the Transmitter Digital Components in Basic Mode Transmitter Phase Compensation FIFO Buffer The transmitter phase compensation FIFO buffer is located at the FPGA logic array interface in the transmitter block and is four words deep The phase compensation FIFO buffer compensates for the phase difference between the clock in the FPGA and the operating clocks in the transceiver block The ...

Page 63: ...most significant byte Altera recommends using the transmitter digital reset to reset the byte serializer FIFO module pointers whenever an unknown state is encountered for example periods when the transmitter PLL unlocks Refer to the Reset Control Power Down chapter for further details on the reset sequence Figure 3 15 demonstrates input and output signals of the byte serializer when serializing a ...

Page 64: ...st be high During reset the running disparity registers are cleared as are the data registers Also the 8B 10B encoder outputs a K28 5 pattern from the RD column continuously until txdigitalreset is low The tx_in and tx_ctrlenable are ignored during the reset state Once out of reset the 8B 10B encoder starts with a bias towards negative disparity RD and transmits three K28 5 code for synchronizing ...

Page 65: ...ntrol code is to be inserted in the encoded data flow When tx_ctrlenable is low the byte at tx_in is encoded as data When tx_ctrlenable is high tx_in is encoded as a control word Figure 3 18 shows that the second 0xBC is encoded as a control code The others are encoded as data Figure 3 18 Control Word Identification Waveform The 8B 10B encoder does not check whether the control code word entered i...

Page 66: ...s of the transceiver in basic mode By default the MegaWizard Plug In Manager parameterizes the altgxb megafunction with the clock configuration shown in Figure 3 19 Figure 3 19 Default Configuration of the altgxb Megafunction in Basic Mode The altgxb megafunction shown in basic mode in Figure 3 19 is configured such that the train receiver PLL with transmitter PLL is enabled The transmitter PLL is...

Page 67: ... separation of receiver and transmitter reference clocks This separation is required if the output reference clock frequency from the transmitter PLL exceeds the 325 MHz phase frequency detector of the receiver PLL For more information on this feature refer to the Stratix GX Analog Description chapter This configuration is shown in Figure 3 20 If double width is used 16 bit bus and the data rate i...

Page 68: ...be optionally enabled to manually feed in a clock from the device buffer write block You can use these options to optimize the global clock usage For example if all transmitter channels between transceiver blocks are from a common clock domain the transceiver instantiations use only one global resource clock instead of one global per transceiver block if the TX_CORECLK option is disabled The situa...

Page 69: ...asic Mode Part 1 of 2 Clock Port Description rx_cruclk Input Input to CRU available as a port when CRU is not trained by the transmitter PLL inclk Input Input to transmitter PLL available as a port when the transmitter PLL is instantiated coreclk_out Output Output clock from transmitter PLL equivalent to TX_PLL_CLK Available as port if transmitter PLL is used rx_clkout Output Output clock from tra...

Page 70: ...ransmitter channel and the receiver channel to the FPGA In basic mode the read port of the transmitter phase compensation FIFO module is either clocked by the CORECLK_OUT or the TX_CORECLK signal The constraint on using TX_CORECLK is that the clock must be frequency locked to the read clock of the transmitter phase compensation FIFO module Synchronous data transfers for a multi transceiver block c...

Page 71: ...regional resource In a multi transceiver block configuration this routing can lead to timing violations because the coreclk_out per transceiver block cannot guarantee phase relationship Therefore the TX_CORECLK with a common clock is recommended for synchronous transmission Transceiver Block 0 Transceiver Block 1 Transceiver Block 2 Transceiver Block 3 PLD Transmit Data Clock Domain coreclk_out 0 ...

Page 72: ...d consider what is fed by the chosen pin Table 3 4 shows the available inter transceiver lines along with the transceiver block that drives them This information is based on the number of transceiver channels in the Stratix GX device Figure 3 23 shows the transceiver routing with respect to inter transceiver lines for the EP1SGX25 device It is important to use this information when placing REFCLKB...

Page 73: ...ansmitter PLL PLD Global Clocks Transceiver Block 1 IQ0 IQ1 Global Clocks I O Bus General Routing Global Clocks I O Bus General Routing IQ2 2 4 4 Receiver PLLs Transmitter PLL Transceiver Block 2 IQ0 IQ1 Global Clocks I O Bus General Routing Global Clocks I O Bus General Routing IQ2 2 4 4 Receiver PLLs Transmitter PLL Transceiver Block 3 IQ0 IQ1 Global Clocks I O Bus General Routing Global Clocks ...

Page 74: ...transceiver block 3 Figure 3 24 Inter Transceiver Line Connections for the EP1SGX40G Device PLD Global Clocks IQ0 IQ1 IQ2 16 Transceiver Block 2 TX PLL IQ0 IQ1 Global Clks I O Bus Gen Routing Global Clks I O Bus Gen Routing IQ2 2 Transceiver Block 3 TX PLL IQ0 IQ1 Global Clks I O Bus Gen Routing Global Clks I O Bus Gen Routing IQ2 2 TX PLL IQ0 IQ1 Global Clks I O Bus Gen Routing Global Clks I O Bu...

Page 75: ...nsiderations Each altgxb megafunction instantiation uses one or more transceiver blocks based on the number of channels that you select There are four channels per transceiver block If a MegaWizard Plug In Manager instantiation uses fewer than four channels the remaining channels in that transceiver block are not available for use Each MegaWizard Plug In Manager instantiation must have similar fun...

Page 76: ...X Analog Description chapter for more information 5 The rxdigitalreset port resets the digital blocks in the receiver channel Each active receiver channel has its own digital reset The txdigitalreset port resets the digital blocks of the transmitter channel Each active transmitter channel has its own digital reset The rxanalogreset port resets the receiver s analog circuits including the receiver ...

Page 77: ...r User Guide Basic Mode Figure 3 26 MegaWizard Plug In Manager ALTGXB Page 4 of 9 General 2 Notes 1 2 Notes to Figure 3 26 1 For more information refer to the Loopback Modes chapter 2 For more information refer to the Stratix GX Built In Self Test BIST chapter ...

Page 78: ...irectly via the rx_bitslip port A low to high transition on the rx_bitslip port enables the word aligner s shift register to slip one bit For example if a 3 bit shift is required to align the incoming byte then rx_bitslip must be toggled low high low high low high The rx_bitslip port can be left in the high or low position after the above sequence 5 The word alignment pattern size must be set to 1...

Page 79: ...re 3 28 1 For more information refer to the Stratix GX Analog Description chapter 2 Data rate versus input clock frequency must adhere to the set multiplication factor of 2 4 5 8 10 16 20 of the input clock Multiplication factors of 2 4 5 must use the dedicated refclkb pins The multiplication factor of 2 also requires that the receiver PLL be trained by the transmitter PLL ...

Page 80: ...x_clkout signal is available per channel 3 The rx_locked signal is an active low signal that indicates that the receiver PLL is phase locked to the reference clock In data mode this signal might be deasserted because the phase is being locked to the data and not the reference clock 4 The rx_syncstatus signal indicates the status of the word aligner Refer to the section Word Aligner on page 3 2 for...

Page 81: ...nuary 2005 Stratix GX Transceiver User Guide Basic Mode Figure 3 30 MegaWizard Plug In Manager ALTGXB Page 8 of 9 Transmitter Note 1 Notes to Figure 3 30 1 For more information refer to the Stratix GX Analog Description chapter ...

Page 82: ...3 36 Altera Corporation Stratix GX Transceiver User Guide January 2005 Basic Mode MegaWizard Plug In Figure 3 31 MegaWizard Plug In Manager ALTGXB Page 9 of 9 Summary ...

Page 83: ...nsceiver in a SONET SDH application requires two types of features protocol specific functions and electrical features Transceiver blocks provide both of these features to a limited extent One example is the protocol feature using A1A2 or A1A1A2A2 for word alignment SONET mode supports a subset of the transceiver blocks to allow for customizable configuration The channel aligner rate matcher and t...

Page 84: ...tes the need to factor in receiver skew margins between the clock and data However with this clocking methodology the word boundary of the re timed data can be altered Stratix GX transceivers offer an Deserializer Serializer Word Aligner 8B 10B Decoder Channel Aligner Byte Deserializer 8B 10B Encoder Phase Compensation FIFO Buffer Reference Clock Reference Clock Phase Compensation FIFO Buffer Rate...

Page 85: ...d aligner does not alter the word boundary Figure 4 3 shows the various components of the word aligner in SONET mode The functionality is described in the following sections Figure 4 3 Stratix GX Word Aligner Components Pattern Detector Module The pattern detector matches the comma to the current byte boundary as specified in the MegaWizard Plug In Manager If the comma is found the optional rx_pat...

Page 86: ... orders and whether the receiver word alignment bit flip option is checked The bit transmission order assumes that if double width mode is used the LSB is transmitted first followed by the MSB In SONET mode the word aligner either aligns to two consecutive 8 bit characters A1A2 or four consecutive 8 bit characters A1A1A2A2 The rx_a1a2size signal differentiates between the 2 and 4 consecutive modes...

Page 87: ... counter A1A2 framing bytes occur every 125 µs based on an STS 1 Frame and a rate of 51 84 Mbps As stated earlier at the rising edge of the rx_enacdet the word aligner locks onto the first comma detected In this scenario the rx_patterndetect is asserted for one clock cycle to signify that the comma has been aligned Also the rx_syncstatus signal is asserted for a clock cycle to signify that the wor...

Page 88: ...fy a re synchronization condition You must deassert and reassert the rx_enacdet signal to re trigger the word aligner The next transition occurs at time n 5 where rx_enacdet is deasserted and the A1 pattern is present on the rx_word_align_out port At time n 6 the A2 pattern is present on the rx_word_align_out port The word aligner then asserts the rx_patterndetect signal for one clock cycle to fla...

Page 89: ...000 value is held at the rx_in port Every rising edge on the rx_bitslip port causes the rx_word_align_out data to shift one bit from the MSB to the LSB At time n 2 the 8 b11110000 data is shifted to a value of 8 b01111000 At this state the rx_patterndetect is held low because the specified comma does not exist in the current word boundary The rx_bitslip is disabled at time n 3 and re enabled at ti...

Page 90: ...signals are fed to the FPGA logic array The signals are sent into the logic array as two 11 bit buses The aggregate bandwidth does not change by use of the Byte Deserializer because the logic array data width is doubled Figure 4 6 demonstrates input and output signals of the byte deserializer when deserializing an 8 bit data input to 16 bits In this case the finishing alignment pattern A2 00010100...

Page 91: ...e Deserializer in 8 16 Bit Mode with Finishing Alignment Pattern in LSB If necessary you might implement logic to perform byte position alignment once data enters the logic array as seen in Figure 4 8 In this example the byte position selection logic determines the proper byte position based on the pattern detect signal inclk data_in 7 0 data_out 15 0 patterndetect 0 patterndetect 1 xxxxxxxx011011...

Page 92: ... read clock is clocked by rx_coreclk You can select rx_coreclk as an optional receiver input port that can also accept a clock supply The clock that feeds the rx_coreclk must be derived from the rx_clkout of its associated receiver channel The receiver phase compensation FIFO buffer can only account for phase differences In SONET mode if you do not select the rx_clkout port the read clock of the r...

Page 93: ...ay interface in the transmitter block and is four words deep The phase compensation FIFO module compensates for the phase difference between the clock in the FPGA and the operating clocks in the transceiver block The read port of the phase compensation FIFO buffer is clocked by the transmitter PLL clock The write clock is clocked by tx_coreclk You can select the tx_coreclk as an optional transmitt...

Page 94: ...nstrates input and output signals of the byte serializer when serializing a 16 bit input to 8 bits The tx_in signal is the input from the FPGA logic array that has already passed through the Transmitter Phase Compensation FIFO module Figure 4 10 Transmitter Byte Serializer in 8 to 16 Bit Mode The LSB is transmitted before the MSB in the transmitter byte serializer Figure 4 10 shows the order of da...

Page 95: ...ment some level of clock domain decoupling can be implemented to interface with a system clock On the transmitter channel the output of the transmitter PLL coreclk_out is sent into the logic array and also loops back to clock the write side of the transmit phase compensation FIFO module The train receiver PLL CRU clock from the transmitter PLL feature can be disabled in the altgxb MegaWizard Plug ...

Page 96: ... from any non REFCLKB pin REFCLKB pins have a 650 MHz limit Figure 4 12 altgxb Megafunction in SONET Mode With Train Receiver CRU From Transmitter PLL Disabled This configuration contains an independent rx_cruclk which feeds the receiver PLL reference clock This input clock port is only available when the receiver PLL is not trained by the transmitter PLL One rx_cruclk is associated with a channel...

Page 97: ...me situation can be optimized for the receiver channels in a single crystal synchronous system with the rx_coreclk Even in a system that is based on a single crystal the recovered clock can still become asynchronous to the system clock during initialization or long run lengths As a result the pointers of the Receiver Phase Compensation FIFO module might overlap and fail to function correctly In si...

Page 98: ...2 Table 4 2 List of Clocking Input Output Ports Available in SONET Mode Part 1 of 2 Clock Port Description rx_cruclk Input Input to CRU available as a port when CRU is not trained by the transmitter PLL inclk Input Input to the transmitter PLL available as a port when the transmitter PLL is instantiated coreclk_out Output Output clock from the transmitter PLL equivalent to TX_PLL_CLK Available as ...

Page 99: ...urations of input and output clocks consider the clocking schemes between inter transceiver blocks carefully to prevent problems later in the design cycle rx_clkout Output Output clock from transceiver In this mode rx_clkout is the recovered clock of the respective channel tx_coreclk Input Clocks the write port of transmitter phase compensation FIFO module Available as an optional port in the Quar...

Page 100: ...he transmitter phase compensation FIFO module is either clocked by the coreclk_out or by the tx_coreclk signal The constraint on using tx_coreclk is that the clock must be frequency locked to the read clock of the transmitter phase compensation FIFO module Synchronous data transfers for a multi transceiver block configuration are accomplished by using the tx_coreclk port The tx_coreclk of multi tr...

Page 101: ...annot guarantee phase relationship For this reason Altera recommends clocking the tx_coreclk with a common clock for synchronous transmission Another inter transceiver block consideration is the selection of the dedicated refclkb pin Stratix GX channels are arranged in banks of four or transceiver blocks Each transceiver block has the ability to share a common reference clock through the inter tra...

Page 102: ...ives them This capability is based on the number of transceiver channels in the Stratix GX device Figure 4 15 shows the transceiver routing with respect to inter transceiver lines It is important to use this information when placing REFCLKB pins For example if a REFCLKB pin is required to feed a transmitter PLL using an IQ line the REFCLKB pin cannot be in transceiver block 1 because IQ2 only feed...

Page 103: ...Receiver PLLs PLD Global Clocks Transceiver Block 1 IQ0 IQ1 Global Clocks I O Bus General Routing Global Clocks I O Bus General Routing Transmitter PLL IQ2 2 4 4 Receiver PLLs Transceiver Block 2 IQ0 IQ1 Global Clocks I O Bus General Routing Global Clocks I O Bus General Routing Transmitter PLL IQ2 2 4 4 Receiver PLLs Transceiver Block 3 IQ0 IQ1 Global Clocks I O Bus General Routing Global Clocks ...

Page 104: ...ne Connections for EP1SGX40G Device PLD Global Clocks IQ0 IQ1 IQ2 16 Transceiver Block 2 Transmitter PLL IQ0 IQ1 Global Clks I O Bus Gen Routing Global Clks I O Bus Gen Routing IQ2 2 Transceiver Block 3 Transmitter PLL IQ0 IQ1 Global Clks I O Bus Gen Routing Global Clks I O Bus Gen Routing IQ2 2 Transmitter PLL IQ0 IQ1 Global Clks I O Bus Gen Routing Global Clks I O Bus Gen Routing IQ2 Transceiver...

Page 105: ...t the altgxb megafunction Altera recommends using the MegaWizard Plug In Manager to instantiate the altgxb megafunction to reduce the chance of invalid settings SONET Mode MegaWizard Considerations Each altgxb megafunction instantiation uses one or more transceiver blocks based on the number of channels that you select There are four channels per transceiver block If a MegaWizard Plug In Manager i...

Page 106: ...escription chapter for more information 5 The rxdigitalreset port resets the digital blocks in the receiver channel Each active receiver channel contains its own digital reset The txdigitalreset port resets the digital blocks of the transmitter channel Each active transmitter channel contains its own digital reset The rxanalogreset port resets the receiver s analog circuits including the receiver ...

Page 107: ...r User Guide SONET Mode Figure 4 18 MegaWizard Plug In Manager ALTGXB Page 4 of 9 General 2 Notes 1 2 Notes to Figure 4 18 1 For more information refer to the Loopback Modes chapter 2 For more information refer to the Stratix GX Built In Self Test BIST chapter ...

Page 108: ... the rx_bitslip port A low to high transition on rx_bitslip port enables the word aligner s shift register to slip one bit For example if a 3 bit shift is required to align the incoming byte rx_bitslip must be toggled low high low high low and high The rx_bitslip can be left in the high or low position after the above sequence 4 The word alignment pattern size in SONET mode is always set to 16 bit...

Page 109: ...The low byte is still transmitted first This feature is used in conjunction with transmitter and word aligner bit flip in SONET mode 2 For more information refer to the Stratix GX Analog Description chapter 3 SONET data rate is set at 2488 32 Mbps by default Other data rates are possible but they must adhere to the set multiplication factor of 2 4 5 8 10 16 20 of the input clock Multiplication fac...

Page 110: ... receiver PLL locked to reference clock 4 Receiver recovered clock output There is one recovered clock available per receiver channel 5 Indicates when the word aligner has aligned to the byte boundary The rx_syncstatus signal goes high for one rx_clkout period when the word aligner aligns to the new byte boundary In 16 bit mode each high and low byte has a separate rx_syncstatus signal 6 Rx_patter...

Page 111: ... Figure 4 22 1 Flips the bit ordering from the FPGA to the transmitter input Bit flip operates on a by byte mode only The low byte and high byte are flipped separately The low byte is still transmitted first This feature is used in conjunction with receiver and word aligner bit flip in SONET mode 2 For more information refer to the Stratix GX Analog Description chapter ...

Page 112: ...4 30 Altera Corporation Stratix GX Transceiver User Guide January 2005 SONET Mode MegaWizard Plug In Manager Figure 4 23 MegaWizard Plug In Manager ALTGXB Page 9 of 9 Summary ...

Page 113: ...MII is composed of 32 transmit channels 32 receive channels 1 transmit clock 1 receive clock 4 transmitter control characters and 4 receive control characters for a 74 pin wide interface in total XAUI on the other hand only consists of 4 differential transmitter channels and 4 differential receiver channels for a 16 pin wide interface in total This reduction in pin count significantly simplifies t...

Page 114: ... and mapped back to the 32 bit XGMII format This process provides a transparent extension of the physical reach of the XGMII and also reduces the interface pin count Logical Link Control LLC MAC Control optional Media Access Control MAC Application Presentation Session Transport Network Data Link Physical OSI Reference Model Layers LAN Carrier Sense Multiple Access Collision Detect CSMA CD Layers ...

Page 115: ...ayer XGXS to XGMII characters as specified in Table 5 1 Figure 5 2 shows an example of the mapping between XGMII characters to the PCS code groups used in XAUI The idle characters are mapped to a pseudorandom sequence of A R and K code groups Table 5 1 XGMII Character to PCS Code Group Mapping Note 1 XGMII TXC XGMII TXD PCD Code Group Description 0 00 through FF Dxx y Normal data transmission 1 07...

Page 116: ...sceiver blocks to support XAUI synchronization channel alignment rate compensation XGMII to PCS code group conversion and PCS code group to XGMII conversion This section describes the supported digital architecture clocking schemes and software implementation of the XAUI mode Figure 5 3 shows a block diagram of a duplex channel configured in XAUI mode XGMII PCS Lane 0 T RXD 7 0 T RXD 15 8 T RXD 23...

Page 117: ...alog Section Digital Section Deserializer Byte Serializer Phase Compensation FIFO Buffer Serializer 8B 10B Encoder Receiver Transmitter Reference Clock Word Aligner Channel Aligner Rate Matcher 8B 10B Decoder Reference Clock Phase Compensation FIFO Buffer Transmitter PLL Receiver PLL Clock Recovery Unit Byte Serializer Analog Section Digital Section Deserializer Reference Clock Word Aligner Channe...

Page 118: ... and synchronization state machines The word aligner cannot be bypassed but if the rx_enacdet signal is not used the word aligner does not alter the data Figure 5 5 shows the various components of the word aligner The functionality of each component is described in the following sections Figure 5 5 Stratix GX Word Aligner Components Pattern Detector Module The pattern detector matches a pre define...

Page 119: ... supported during the synchronization stage XAUI Synchronization Mode When a Stratix GX transceiver is configured to the XAUI protocol the built in pattern detector word aligner and XAUI state machines adhere to the PCS synchronization specification The code group synchronization is achieved upon the reception of four K28 5 commas Each comma is followed by any number of valid code groups Invalid c...

Page 120: ...r Guide January 2005 XAUI Mode Receiver Architecture Figure 5 6 IEEE 802 3ae PCS Synchronization State Diagram Note to Figure 5 6 1 lane_sync_status n signal_detect n and signal_detectCHANGE n refer to the number of the received lane n where n 0 to 3 ...

Page 121: ... code group referred to as A The A code group is transmitted simultaneously on all four lanes constituting an A ordered set during idles or inter packet gaps IPG XAUI receivers use these code groups to resolve any lane to lane skew Skew between the lanes can be up to 40 UI 12 8ns as specified in the standard which relaxes the board design constraints Figure 5 7 shows lane skew at the receiver inpu...

Page 122: ...5 10 Altera Corporation Stratix GX Transceiver User Guide January 2005 XAUI Mode Receiver Architecture Figure 5 8 IEEE802 3ae PCS Deskew State Diagram ...

Page 123: ...m between crystals Stratix GX transceivers have embedded circuitry to perform clock rate compensation This is achieved by the insertion or removal of the PCS SKIP code group R from the inter packet gap IPG or idle stream This process is called rate matching and is sometimes referred to as clock rate compensation The rate matcher in Stratix GX transceivers consists of a 12 word deep FIFO module alo...

Page 124: ...ting reset the 8B 10B decoder can start with either a positive or negative disparity The decoder calculates the initial running disparity based on the first valid code received The receiver block must be word aligned after reset before the 8B 10B decoder can decode valid data or control codes Code Error Detect The rx_errdetect signal indicates when the code received contains an error This port is ...

Page 125: ...ct signal also transitions high Figure 5 10 shows a case where the disparity is violated A K28 5 code has an 8 bit value of 8 hbc and a 10 bit value jhgfiedcba The 10 bit value is 10 b0011111010 10 h17c for RD or 10 b1100000101 10 h283 for RD Assume that the running disparity at time n 1 is negative so the expected code at time n is from the RD column Since a K28 5 does not have a balanced 10 bit ...

Page 126: ... demonstrating the detection of a K28 5 code BC ctrl The rx_ctrldetect 1 b1 is aligned with 8 hbc which indicates that this code is a control code The reset of the code received is data Figure 5 11 Control Code Detection clock rx_out 7 0 rx_disperr 07 07 07 07 07 07 rx_ctrldetect 07 Expected RD code rx_in 17C 283 17C 283 283 283 17C 17C RD RD RD RD RD RD RD RD RD code received RD RD RD RD RD RD RD...

Page 127: ...its The byte deserializer does not process the data and therefore the control signals fed to the module are simply processed to match the latency to the data The byte deserializer in the receiver block takes in up to 13 bits It is possible to feed the following to the byte deserialzer 8 bits of data and up to 2 control signals rx_patterndetect rx_syncstatus 8 bits of data and up to 5 control signa...

Page 128: ...gate bandwidth does not change by using the byte deserializer because the logic array data width is doubled Figure 5 12 demonstrates input and output signals of the byte deserializer when deserializing an 8 bit data input to 16 bits In this case the alignment pattern A 10111100 is located in the MSB of the 16 bit output and this is reflected with patterndetect 1 going high The output of the byte d...

Page 129: ...the proper byte position based on the pattern detect signal Figure 5 14 Receiver Byte Deserializer Data Recovery in Logic Array xxxxxxxx01101111 inclk data_out 15 0 patterndetect 1 11111000 10111100 11000110 data_in 7 0 11110001 10101010 11001100 patterndetect 0 B C D E F A BA DC 10111100 11000110 11110001 10101010 Gigabit Transceiver Block Logic Array D Q D Q rx_out 17 10 rx_out 7 0 Byte Boundary...

Page 130: ... phase compensation FIFO module is always used and cannot be bypassed XAUI Mode Transmitter Architecture Figure 5 15 diagrams the transmitter digital components in XAUI mode Figure 5 15 Block Diagram of Transmitter Digital Components in XAUI Mode Transmitter Phase Compensation FIFO Module The Transmitter Phase Compensation FIFO module is located at the FPGA logic array interface in the transmitter...

Page 131: ...Serializer The byte serializer in the transmitter block takes a 16 bit input from the FPGA logic array and serializes it to 8 bits It transmits from the least significant byte to the most significant byte The transmitter digital reset must always be used to reset the FIFO module pointers whenever an unknown state is encountered such as when the transmitter PLL loses lock Refer to the chapter Reset...

Page 132: ...ion is shown in Figure 5 17 Figure 5 17 IEEE 802 3ae PCS Transmit Source State Diagram SEND_RANDOM_R tx_code group 39 0 R PUDR SEND_DATA IF TX T THEN cvtx_terminate tx_code group 39 0 ENCODE TX PUDR reset TX IDLE TX Q SEND_A tx_code group 39 0 A next_ifg K PUDR SEND_Q tx_code group 39 0 TQMSG Q_det false PUDR SEND_RANDOM_A tx_code group 39 0 A PUDR SEND_RANDOM_K tx_code group 39 0 K PUDR SEND_K tx...

Page 133: ...r to 8B 10B Code on page 10 1 The 8B 10B encoder translates the 8 bit data or 8 bit control character to its 10 bit equivalent The conversion format is shown in Figure 5 18 The10 bit resultant data is transmitted LSB first by the serializer Table 5 4 XGMII Character to PCS Code Group Mapping Note 1 XGMII XGMII TXD PCS Code Group Description 0 00 though FF Dxx y Normal data transmission 1 07 K28 0 ...

Page 134: ...d transmits three K28 5 codes for synchronizing before it starts encoding and transmitting the data on tx_in If the reset for the 8B 10B encoder is asserted the 8B 10B decoder receiving the data may receive an invalid code error sync error control detect and or disparity error while txdigitalreset is high Figure 5 19 shows the reset behavior of the 8B 10B encoder When in reset txdigitalreset is hi...

Page 135: ...s a control word The waveform in Figure 5 20 shows that 0x07 is encoded as a control code The other values of tx_in are encoded as data Figure 5 20 Control Word Identification Waveform The 8B 10B encoder does not check to see if the code word that is entered is one of the 12 valid codes If an invalid control code is entered the resulting 10 bit code might be encoded as an invalid code which does n...

Page 136: ...transceiver block when XAUI mode is selected The MegaWizard Plug In Manager also offers clock options other than the default selection which facilitates the clocking scheme Figure 5 21 shows that the altgxb megafunction is configured such that the train receiver PLL with transmitter PLL is enabled The transmitter PLL is fed from an inclk port that can itself be fed from a dedicated REFCLKB global ...

Page 137: ...LL You can use this feature to support additional multiplication factors for the receiver PLL because it supports the separation of receiver and transmitter reference clocks This separation is necessary if the output reference clock frequency from the transmitter PLL exceeds the 325 MHz phase frequency detector of the receiver PLL see Chapter 2 Stratix GX Analog Description for more information Th...

Page 138: ...ion to optimize the global clock usage For instance if all transmitter channels between transceiver blocks are from a common clock domain the transceiver instantiations use a total of one global resource instead of one global per transceiver block if the tx_coreclk option is not enabled On the transmitter functionality screen under the optional port of transmitter section if tx_coreclk is selected...

Page 139: ...Table 5 5 describes the input and output ports shown in Figure 5 23 Table 5 5 List of Input Output Ports Available in XAUI Mode Clock Port Description inclk Input Input to the transmitter PLL Available as a port when the transmitter PLL is instantiated rx_cruclk Input Input to CRU Available as a port when CRU is not trained by the transmitter PLL tx_coreclk Input Clocks write port of the transmitt...

Page 140: ...I mode depending on the options set in the MegaWizard Plug In Manager you can use either the coreclk_out or tx_coreclk clock to send the data into the transmit of the transceiver However the tx_coreclk must be frequency locked with the transmit system clock of each transceiver block In each transceiver block one transmitter PLL is shared among four transmitters In a multi transceiver block scenari...

Page 141: ...nding across the transceiver blocks used in Stratix GX devices to ensure that there is no skew between the transceiver blocks if each transceiver is operating no channel bonding is required and the data can simply go to destination registers as shown in Figure 5 25 Also all traces in your design should match ALTGXB PLD Transceiver Block 0 Transceiver Block 1 coreclk_out 0 tx_coreclk 0 tx_coreclk 1...

Page 142: ...ver block situation data striping across the channels is common Skew introduced between transceiver blocks by passive and active elements of the link must be de skewed in the PLD core channel alignment to ensure error free data ALTGXB PLD Transceiver Block 0 Transceiver Block 1 Transceiver Block 2 Transceiver Block 3 coreclk_out 3 coreclk_out 0 rx_out 15 0 coreclk_out 1 rx_out_1 15 0 coreclk_out 2...

Page 143: ...s the available IQ lines and which transceiver blocks are driven by refclkb This information is based on the number of transceiver channels in the Stratix GX device Figure 5 26 shows the transceiver routing with respect to Inter Transceiver lines This information is vital when placing refclkb pins When placing refclkb pins see Appendix C REFCLKB Pin Constraints for information about analog reads a...

Page 144: ...rmation about analog reads and refclkb pin usage constraints 16 IQ0 IQ1 IQ2 Transceiver Block 0 IQ0 IQ1 Global Clocks I O Bus General Routing Global Clocks I O Bus General Routing Transmitter PLL IQ2 2 4 4 Receiver PLLs PLD Global Clocks Transceiver Block 1 IQ0 IQ1 Global Clocks I O Bus General Routing Global Clocks I O Bus General Routing Transmitter PLL IQ2 2 4 4 Receiver PLLs Transceiver Block ...

Page 145: ...Routing Global Clks I O Bus Gen Routing IQ2 2 Transceiver Block 3 TX PLL IQ0 IQ1 Global Clks I O Bus Gen Routing Global Clks I O Bus Gen Routing IQ2 2 TX PLL IQ0 IQ1 Global Clks I O Bus Gen Routing Global Clks I O Bus Gen Routing IQ2 Transceiver Block 0 2 Transceiver Block 1 TX PLL IQ0 IQ1 Global Clks I O Bus Gen Routing Global Clks I O Bus Gen Routing IQ2 2 TX PLL IQ0 IQ1 Global Clks I O Bus Gen ...

Page 146: ...atix GX block directly by calling out the altgxb megafunction Altera recommends using the MegaWizard Plug In Manager to instantiate the altgxb megafunction to reduce the chance of invalid settings XAUI Mode MegaWizard Considerations Each altgxb MegaWizard instantiation can use one or more transceiver blocks based on the number of channels you select There are four channels per transceiver block In...

Page 147: ...nalog Description chapter 7 The rxdigitalreset port resets the digital blocks in the receiver channel Each active receiver channel has its own digital reset The txdigitalreset port resets the digital blocks of the transmitter channel Each active transmitter channel has its own digital reset The rxanalogreset signal resets the receiver s analog circuits including the receiver PLL Each active receiv...

Page 148: ...XAUI Mode MegaWizard Plug In Manager Figure 5 29 MegaWizard Plug In Manager ALTGXB Page 4 of 9 General 2 Notes 1 2 Notes to Figure 5 29 1 For more information refer to the Loopback Modes chapter 2 For more information refer to the Stratix GX Built In Self Test BIST chapter ...

Page 149: ...e 5 30 MegaWizard Plug In Manager ALTGXB Page 5 of 9 Receiver 1 Notes 1 2 Notes to Figure 5 30 1 For more information refer to the Stratix GX Analog Description chapter 2 Word aligner in XAUI mode is always set as a 10 bit K28 5 pattern Both positive and negative disparities are checked ...

Page 150: ...x GX Analog Description chapter The Force Signal Detect option is always on and cannot be turned off Because the signal detect circuitry is always forced the rx_signaldetect is always set in XAUI mode 3 XAUI Data Rate is set to 3125 Mbps by default Other data rates are possible but they must adhere to the set multiplication factor of 2 4 5 8 10 16 20 of the input clock Multiplication factors of 2 ...

Page 151: ...ed the rx_signaldetect signal is always set in XAUI and GIGE modes supporting backward compatibility with existing designs See the Stratix GX Analog Description chapter for additional information 4 Indicates when the word aligner has aligned to the byte boundary The rx_syncstatus signal goes high for one rx_clkout period when the word aligner aligns to the new byte boundary If in 16 bit mode each ...

Page 152: ...er Notes 1 2 Notes to Figure 5 33 1 For more information refer to the Stratix GX Analog Description chapter 2 tx_coreclk You can optionally choose the write clock of the transmitter phase comp FIFO buffer This clock should be frequency locked with the internal reference clock because the phase comp FIFO buffer cannot tolerate frequency variations and contains no error flags ...

Page 153: ...Altera Corporation 5 41 January 2005 Stratix GX Transceiver User Guide XAUI Mode Figure 5 34 MegaWizard Plug In Manager ALTGXB Page 9 of 9 Summary ...

Page 154: ...5 42 Altera Corporation Stratix GX Transceiver User Guide January 2005 XAUI Mode MegaWizard Plug In Manager ...

Page 155: ...ion on transmit The GMII is an intermediate or parallel interface that connects the PCS sub layer with the media access control MAC in a system that supports GigE mode The GigE physical layer is divided into three sub layers the PCS the PMA and the physical medium dependent PMD layers If you implement a GMII compliant interface that interface offers data rates up to 1 000 Mbps at either half or fu...

Page 156: ... groups for the reference of idle ordered sets and configuration ordered sets as explained in the Idle Generation section For full details on the GigE standard and code group functionality refer to clause 36 in the Gigabit Ethernet standard IEEE 802 3 The remaining functions of the PCS auto negotiation collision detect and carrier detect must be implemented in user logic or external circuits if th...

Page 157: ... 7 T End_of_Packet 1 K29 7 V Error_Propagation 1 K30 7 Note to Table 6 1 1 Two data code groups represent the Config_Reg value Table 6 1 GigE Code Groups Part 2 of 2 Note 1 Code Ordered Set Number of Code Groups Encoding Word Aligner Phase Compensation FIFO Buffer Deserializer Serializer 8B 10B Decoder Channel Aligner Byte Deserializer 8B 10B Encoder Reference Clock Reference Clock Byte Serializer...

Page 158: ...O buffer Word Aligner The word aligner is composed of a pattern detector and synchronization state machines The word aligner cannot be bypassed but if the application is not using the rx_enacdet signal the word aligner does not alter the data Figure 6 4 shows the various components of the word aligner The Pattern Detector Module and Synchronization State Machines sections describe the functionalit...

Page 159: ...ires synchronization to align the byte boundary of the receiver after incoming serial data is de serialized This step is necessary because the Stratix GX block uses a non source synchronous serial stream To correctly align the byte boundary at the receiver the Stratix GX device sends a unique synchronization pattern to the receiver that does not occur between any Dx y or Kx y code combinations nam...

Page 160: ...to 10 even though a 7 bit comma string 7 b0011111 as a comma or 7 b1100000 as a comma is allowed as stated in the IEEE 802 3 specification This 7 bit comma is part of the K28 1 K28 5 and K28 7 code groups Use a 10 bit K28 5 code group to prevent a 7 bit comma from being detected across boundaries when a K28 7 code is followed by a K28 x D3 x D11 x D12 x D19 x D20 x or D28 x code group where x is a...

Page 161: ...entially alter the code group boundary The boundaries of the code groups are re aligned through a synchronization process specified in the IEEE 802 3 standard Synchronization State Machines Synchronization occurs when the receiver sees three consecutive ordered sets An ordered set defined for synchronization is a K28 5 comma followed by any odd number of valid data code groups Dx y Although you ca...

Page 162: ...6 8 Altera Corporation Stratix GX Transceiver User Guide January 2005 GigE Mode Receiver Architecture Figure 6 7 Synchronization Diagram State Machine ...

Page 163: ...ositive disparity K28 5 10 h17C followed by a negative disparity D16 2 10 h289 code group The I2 ordered set can start the idle sequence if the disparity before the idle sequence is negative Otherwise I2 follows an I1 ordered set and is continually transmitted maintaining a negative running disparity until the end of the IPG Figure 6 8 shows a case in which the idle stream starts with an I1 follow...

Page 164: ...an I2 ordered set is deleted as shown in Figure 6 10 If the rate matching FIFO buffer encounters an almost empty condition an I2 ordered set will be added as shown in Figure 6 11 The position of the I2 ordered set that is added to or deleted from the idle stream varies depending on when the rate matcher encounters the almost full or almost empty condition Figure 6 10 Detection of an I2 Ordered Set...

Page 165: ...izer receives the least significant bit LSB of the 10 bit encoded code first and the most significant bit MSB last The data received must be from the supported Dx y or Kx y list All 8B 10B control signals disparity error control detect and code error are pipelined with the data in the Stratix GX receiver block and are edge aligned with the data Figure 6 12 is a diagram of the 10 bit to 8 bit conve...

Page 166: ...ed The disparity error is indicated at the optional rx_disperr port The current running disparity is based on the disparity calculation of the last code received The disparity calculation is described in the 8B 10B code section in the Appendix If negative disparity is calculated for the last 10 bit code a neutral or positive disparity 10 bit code is expected If the decoder does not receive a neutr...

Page 167: ...ity K28 5 code from the RD column is expected at time n 5 Figure 6 13 Disparity Error Control Detect The 8B 10B decoder differentiates between data and control codes using the rx_ctrldetect port Although this port is optional there is no way of differentiating a Dx y code group from a Kx y code group if the port is unused Figure 6 14 shows an example waveform demonstrating the receipt of a K28 5 c...

Page 168: ... In GigE mode the write port is clocked by the refclk from the transmitter phase locked loop PLL The read clock is clocked by CORECLK output from the transmitter PLL The receiver phase compensation FIFO buffer can only account for phase differences and must be derived from the recovered clock of its associated channel The receiver phase compensation FIFO buffer is always used and you cannot bypass...

Page 169: ...tput clock refclk clocks the read port of the phase compensation FIFO buffer The TX_CORECLK port clocks the write clock You can select the TX_CORECLK port as an optional transmitter input port to use as a write side clock of the FIFO buffer Make sure that there is no frequency difference between the TX_CORECLK port and the transmitter PLL clock The transmitter phase compensation FIFO only accounts...

Page 170: ... 16 shows an example of the GigE synchronization pattern Although the example shows one D0 0 8 h00 as the Dx y code any Dx y and any odd number of Dx y can be used Figure 6 16 Example of a GigE Synchronization Transmit Pattern Idle Generation In GigE mode the transmitter replaces any Dx y code group following a K28 5 comma with either a D5 6 8 hc5 or a D16 2 8 h50 depending on the current running ...

Page 171: ...6 17 Input Data Codes vs Output Data Codes 8B 10B Encoder The 8B 10B encoder is part of the Stratix GX transceiver block The 8B 10B encoder translates 8 bit data and a 1 bit control identifier by using the tx_ctrlenable signal into a 10 bit DC balanced data stream For more information about the 8B 10B code refer to the 8B 10B Code section in the Appendix The 8B 10B encoder translates the 8 bit dat...

Page 172: ... of three automatically sent K28 5 commas and the first user sent Dx y code groups are considered as one idle ordered set This fact can be a problem if there are even numbers of Dx y code groups transmitted before the start of the synchronization sequence Figure 6 19 shows an example of an even number of Dx y code groups between the last automatically sent K28 5 comma and the first user sent K28 5...

Page 173: ...ered is one of the 12 valid codes If an invalid control code is entered the resulting 10 bit code is encoded as either invalid code that does not map to a valid Dx y or Kx y code or valid Dx y code depending on the value entered An example is the invalid encoding of a K24 1 data 8 h38 tx_ctrlenable 1 b1 Depending on the current running disparity the K24 1 can be encoded to be 10 b0110001100 0x18C ...

Page 174: ...cking details and the external clock ports in GigE mode Each block diagram shows the input and output port clocks The MegaWizard Plug In Manager by default selects a set of clocks for transmitters and receivers in a transceiver when GigE mode is selected The wizard also offers clock options other than default to facilitate your clocking schemes Figure 6 21 Default Configuration of altgxb Megafunct...

Page 175: ... transmitter PLL On the transmitter channel the output of the transmitter PLL coreclk_out is sent from the logic array as an output and also loops back to clock the write side of the transmit phase compensation FIFO buffer in this case software automatically routes the connection and the read side of the receive phase compensation FIFO buffer The training receiver PLL clock recovery unit CRU clock...

Page 176: ...d by Adding RX_CRUCLK If the TX_CORECLK is enabled the training receiver CRU clock from transmitter PLL is not enabled and other default options are also enabled this configuration has an independent rx_cruclk port that feeds the receiver PLL reference clock This input clock port is available only when the receiver PLL is not trained by the transmitter PLL ...

Page 177: ...k rclk fclk or logic array routing if CORECLK_OUT must be used Alternatively TX_CORECLK is supplied from a crystal or any other clock source as long as it is frequency locked to the read side of the phase compensation FIFO buffer on the transmit side In multicrystal environments individual recovered clocks need to drive the read clock of the phase compensation FIFO The Quartus II software does thi...

Page 178: ...3 1 The RX_CORECLK port is enabled for the rate matching FIFO buffer Table 6 2 summarizes the clocks that are used in GigE mode Table 6 2 Clocks in GigE Mode Part 1 of 2 Clock Port Description INCLK Input Input to transmitter PLL Available as a port when transmitter PLL is instantiated RX_CRUCLK Input Input to CRU Available as a port when CRU is not trained by transmitter PLL ...

Page 179: ...el to the PLD In GigE mode the read port of the transmitter phase compensation FIFO buffer can either be clocked by the CORECLK_OUT or the TX_CORECLK port The constraint on using TX_CORECLK port is that the clock must be frequency locked to the read port of the transmitter phase compensation FIFO buffer Synchronous data transfers for a multi transceiver configuration are accomplished with the TX_C...

Page 180: ...mission Another inter transceiver consideration is the selection of the dedicated REFCLKB pin Stratix GX channels are arranged in banks of four called transceiver blocks Each transceiver block has the ability to share a common reference clock through the inter transceiver lines IQ lines The Stratix GX logic array clock usage can be reduced by using the IQ lines The IQ lines are used when a REFCLKB...

Page 181: ... placing REFCLKB pins When placing refclkb pins see Appendix C REFCLKB Pin Constraints for information about analog reads and refclkb pin usage constraints For example if a REFCLKB pin is required to feed a transmitter PLL using an inter transceiver line the REFCLKB pin cannot be in transceiver block 1 because IQ2 only feeds the receiver PLLs Table 6 3 REFCLKB Pin to Inter Transceiver Line Connect...

Page 182: ... 4 4 Receiver PLLs PLD Global Clocks Transceiver Block 1 IQ0 IQ1 Global Clocks I O Bus General Routing Global Clocks I O Bus General Routing Transmitter PLL IQ2 2 4 4 Receiver PLLs Transceiver Block 2 IQ0 IQ1 Global Clocks I O Bus General Routing Global Clocks I O Bus General Routing Transmitter PLL IQ2 2 4 4 Receiver PLLs Transceiver Block 3 IQ0 IQ1 Global Clocks I O Bus General Routing Global Cl...

Page 183: ...ch is in the middle of all the transceiver blocks as illustrated Be sure to use this information when placing REFCLKB pins When placing refclkb pins see Appendix C REFCLKB Pin Constraints for information about analog reads and refclkb pin usage constraints For example if a REFCLKB pin is required to feed a transmitter PLL using an inter transceiver line the REFCLKB pin cannot be in transceiver blo...

Page 184: ... IQ0 IQ1 Global Clks I O Bus Gen Routing Global Clks I O Bus Gen Routing IQ2 2 TX PLL IQ0 IQ1 Global Clks I O Bus Gen Routing Global Clks I O Bus Gen Routing IQ2 Transceiver Block 0 2 Transceiver Block 1 TX PLL IQ0 IQ1 Global Clks I O Bus Gen Routing Global Clks I O Bus Gen Routing IQ2 2 TX PLL IQ0 IQ1 Global Clks I O Bus Gen Routing Global Clks I O Bus Gen Routing IQ2 Transceiver Block 4 2 4 4 4 ...

Page 185: ... Altera recommends that you use the MegaWizard Plug In Manager to instantiate your altgxb megafunction to reduce the chance of invalid settings GigE Mode MegaWizard Considerations Each altgxb MegaWizard instantiation can use one or more transceiver blocks based on the number of channels you select There are four channels per transceiver block If a MegaWizard instantiation uses fewer than four chan...

Page 186: ...the channel s transceiver input and output pins 3 8 bits single width 4 For more information refer to the Stratix GX Analog Description chapter 5 rxdigitalreset resets the digital blocks in the receiver channel Each active receiver channel has its own digital reset txdigitalreset resets the digital blocks of the transmitter channel Each active transmitter channel has its own digital reset rxanalog...

Page 187: ...eiver User Guide GigE Mode Figure 6 28 MegaWizard Plug In ALTGXB Page 4 of 9 General 2 Notes 1 2 Notes to Figure 6 28 1 For more information refer to the Loopback Modes chapter 2 For more information refer to the Stratix GX Built In Self Test BIST chapter ...

Page 188: ...Manager ALTGXB Page 5 of 9 Receiver 1 Notes 1 3 Notes to Figure 6 29 1 Enable this if the device is an engineering sample device 2 For more information refer to the Stratix GX Analog Description chapter 3 The word aligner in GigE mode is always set as a 10 bit K28 5 pattern Both positive and negative disparities are checked ...

Page 189: ... GigE data rate is set to 1250 Mbps by default Possible multiplication factors of the input clock are 2 4 5 8 10 16 and 20 Multiplication factors of 2 4 and 5 must use the refclkb pins A multiplication factor of 2 also requires that the receiver PLL be trained by the transmitter PLL 3 The force signal detection option is always on you cannot turn it off Because the signal detect circuitry is alway...

Page 190: ...erence clock 3 The rx_signaldetect is only available in XAUI or GigE mode Refer to the Stratix GX Analog Description chapter for additional information 4 Indicates when the word aligner has aligned to the byte boundary The rx_syncstatus signal goes high for one rx_clkout period when the word aligner aligns to the new byte boundary 5 The rx_patterndetect is similar to the rx_syncstatus with the exc...

Page 191: ...Notes to Figure 6 32 1 For more information refer to the Stratix GX Analog Description chapter 2 tx_coreclk You can optionally choose the write clock of the transmitter phase comp FIFO buffer This clock should be frequency locked with the internal reference clock because the phase comp FIFO buffer cannot tolerate frequency variations and contains no error flags ...

Page 192: ...ion language HDL Design Description When the protocol is specified as GigE synchronization is achieved on receiving three K28 5 Dx y ordered sets Each K28 5 is separated by any odd number of Dx y code groups Invalid code groups are not supported during the synchronization stage If at any time four invalid code groups are received separated by fewer than three valid code groups synchronization is l...

Page 193: ...r kdata txdata reg tff wire 7 0 rxout wire coreclk rxclk rx_in wire patterndetect ctrldetect errdetect syncstatus disperr GXB instantiation gige8b10bgxb gige8b10bgxb_inst pll_areset 1 b0 pllenable 1 b1 inclk clk rx_in rx_in rx_slpbk 1 b1 rxanalogreset 1 b0 tx_in txdata tx_ctrlenable txctrl rxdigitalreset reset txdigitalreset 1 b0 rx_disperr disperr rx_patterndetect patterndetect rx_ctrldetect ctrl...

Page 194: ...5 6 kdata 8 hdc k28 6 7 kdata 8 hfc k28 7 8 kdata 8 hf7 k23 7 9 kdata 8 hfb k27 7 10 kdata 8 hfd k29 7 11 kdata 8 hfe k30 7 12 kdata 8 hff invalid code default kdata 8 hbc endcase always globalcntr or curst case globalcntr 0 nextst reset resets receiver 1 nextst sync sends out 3 idle ordered sets 8 nextst count sending counter values 40 nextst txk sending control characters 52 nextst count sending...

Page 195: ...and D31 7 begin reset 0 if globalcntr 0 1 begin txdata 8 hbc txctrl 1 end else begin txdata 8 hff txctrl 0 end end tx_err sends an out of bounds control code K31 7 begin reset 0 txctrl 1 txdata 8 hff end count sends out value of a counter begin reset 0 txctrl 0 txdata datacntr end txk sends out all 12 K codes begin reset 0 txctrl 1 txdata kdata end default begin reset 0 txctrl 0 txdata datacntr en...

Page 196: ...lk input 0 0 rx_in input 0 0 rx_slpbk input 0 0 rxanalogreset input 7 0 tx_in input 0 0 tx_ctrlenable input 0 0 rxdigitalreset input 0 0 tx_forcedisparity input 0 0 txdigitalreset output 0 0 rx_disperr output 0 0 rx_patterndetect output 0 0 rx_ctrldetect output 0 0 tx_out output 0 0 rx_errdetect output 0 0 coreclk_out output 7 0 rx_out output 0 0 rx_syncstatus wire 0 0 sub_wire0 wire 0 0 sub_wire1...

Page 197: ...param altgxb_component force_disparity_mode ON altgxb_component channel_width 8 altgxb_component pll_inclock_period 7812 altgxb_component use_symbol_align ON altgxb_component rx_ppm_setting 1000 altgxb_component pll_bandwidth_type LOW altgxb_component dwidth_factor 1 altgxb_component number_of_channels 1 altgxb_component vod_ctrl_setting 1000 altgxb_component align_pattern_length 10 altgxb_compone...

Page 198: ...tgxb_component number_of_quads 1 endmodule Simulation Waveform Hardware Verification Results Figures 6 34 and 6 35 show the complete synchronization sequence from the transmitter to the receiver for the SignalTap II logic analyzer and the Quartus II software respectively The GigE duplex channel is configured in a serial loopback mode The synchronization pattern is sent by the transmitter The recei...

Page 199: ... analyzer and the Quartus II software respectively On receiving four invalid codes that are separated by fewer than three valid codes the receiver signals a loss of synchronization by deasserting the rx_syncstatus signal and sending a K28 4 code group 8 h9C ctrl In the example four invalid codes are transmitted with zero valid codes in between Figure 6 36 Loss of Synchronization SignalTap II Logic...

Page 200: ...6 46 Altera Corporation Stratix GX Transceiver User Guide January 2005 Design Example ...

Page 201: ... the FPGA logic array and has the option of using all the blocks in the transmitter The data then traverses from the transmitter in serial form to the receiver The serial data is the data that is transmitted from the Stratix GX device Once the data enters the receiver in serial form it can use any of the receiver blocks and is then fed into the FPGA logic array The PRBS block generates data when u...

Page 202: ...er the deserializer and has the option of using any of the subsequent receiver blocks before being output by the receiver into the FPGA logic array The PRBS block generates data When using parallel loopback the tx_out ports are active and the differential output voltage on the tx_out ports is based on the current setting in the Quartus II software or on the user setting Non Active Path Active Path...

Page 203: ...nabled on a channel by channel basis using the tx_srlpbk port When using reverse serial loopback the VOD must be 400mV When tx_srlpbk is high all blocks that are active when the signal is low are still active The reverse serial loopback is enabled but the logic array is still seeing data Reverse serial loopback is often implemented when using a Bit Error Rate Tester BERT Clock Recovery Unit Word A...

Page 204: ...rse Serial Loopback Mode Non Active Path Active Path Clock Recovery Unit Deserializer BIST PRBS Verifier BIST Incremental Verifier BIST Generator Byte Deserializer Phase Compensation FIFO Byte Serializer BIST PRBS Generator 8B 10B Encoder Serializer Phase Compensation FIFO 8B 10B Decoder Rate Matcher Channel Aligner Word Aligner ...

Page 205: ... Notes to Figure 8 1 1 rx_slpbk is required in PRBS and incremental BIST modes 2 rx_bisterr and rx_bistdone are only available in PRBS and incremental BIST modes The BIST data generator is configured to generate pseudo random binary sequence PRBS incremental high frequency low frequency or mixed frequency patterns The BIST verifier supports only the PRBS and Incremental modes The remaining BIST mo...

Page 206: ...of the data transmission paths The PRBS generator is used in 8 16 10 or 20 bit modes In 8 or 16 bit data width modes the PRBS generator generates 28 1 unique patterns In 10 or 20 bit data modes the PRBS generator yields 210 1 unique patterns Table 8 1 lists the modes and their associated polynomials BIST MODES PATTERN GENERATOR Transmitter PRBS INCREMENTAL HIGH Frequency PATTERN VERIFIER Receiver ...

Page 207: ...er the what self test mode do you want to use option in the Quartus II software In this mode the BIST generator sends out the data pattern in the following sequence K28 5 comma K27 7 Start of Frame SOF Data 00 FF incremental K28 0 K28 1 K28 2 K28 3 K28 4 K28 6 K28 7 K23 7 K30 7 K29 7 End of Frame EOF and repeat The 8b 10b encoder must be enabled for proper operation Because the 8 b10b encoder is e...

Page 208: ... K28 7 character 8 b11111100 into the 8b 10b encoder to generate a 10 b0011111000 or 10 b1100000111 low frequency character The low frequency data transition toggles at one tenth the data rate of the high frequency pattern Like the high frequency pattern the low frequency pattern is DC balanced with the number of ones equal to the number of zeros This fact is important when trying to perform a fir...

Page 209: ... encoder in order to generate the mixed frequency pattern Pattern Verifier The BIST verifier supports the PRBS and incremental modes PRBS Mode Verifier The PRBS verifier provides a quick check through the non 8b 10b path of the transceiver block You must select the internal or external loopback mode to loop the generated data back into the verifier in the receiver Select either a serial or paralle...

Page 210: ...nize After synchronization the BIST verifier checks for the following sequence K27 7 SOF Data 00 FF incremental K28 0 K28 1 K28 2 K28 3 K28 4 K28 6 K28 7 K23 7 K30 7 and K29 7 EOF If it does not see a K27 7 SOF within 31 patterns the rx_errdetect and rx_bistdone signals go high and the verifier stops The verifier checks for this sequence twice before setting the rx_bistdone signal high If any erro...

Page 211: ... to the 28 1 by changing the data width mode comma and word alignment mode as listed in Table 8 2 on page 8 6 A useful circuit to include in the PRBS verifier is a self timed reset controller This controller prevents bounce conditions that might occur when an external switch is used This design consists of a reset module reset v that periodically toggles the rxdigitalreset signal of the altgxb ins...

Page 212: ...nclk inclk rx_in rx_in rx_slpbk VCC rxdigitalreset reset_wire coreclk_out coreclk_out rx_bistdone rx_bistdone rx_bisterr rx_bisterr rx_clkout rx_clkout tx_out tx_out Reset Module Instantiation reset_mod reset_mod_inst clk inclk reset reset_wire endmodule Reset Module Design reset_mod v module reset_mod clk reset input clk output reset reg 19 0 counter reg reset always posedge clk counter counter 1...

Page 213: ...rx_slpbk input 0 0 rxdigitalreset output 0 0 tx_out output 0 0 coreclk_out output 0 0 rx_clkout output 0 0 rx_bistdone output 0 0 rx_bisterr wire 0 0 sub_wire0 wire 0 0 sub_wire1 wire 0 0 sub_wire2 wire 0 0 sub_wire3 wire 0 0 sub_wire4 wire 0 0 tx_out sub_wire0 0 0 wire 0 0 coreclk_out sub_wire1 0 0 wire 0 0 rx_clkout sub_wire2 0 0 wire 0 0 rx_bistdone sub_wire3 0 0 wire 0 0 rx_bisterr sub_wire4 0...

Page 214: ... altgxb_component equalizer_ctrl_setting 0 altgxb_component use_auto_bit_slip ON altgxb_component use_rate_match_fifo OFF altgxb_component signal_threshold_select 80 altgxb_component self_test_mode 0 altgxb_component use_double_data_mode ON altgxb_component use_preemphasis_ctrl_signal OFF altgxb_component protocol CUSTOM altgxb_component clk_out_mode_reference ON altgxb_component rx_bandwidth_type...

Page 215: ...ts for this PRBS BIST test Figure 8 4 SignalTap II Logic Analyzer Results for PRBS BIST Test Design Design 2 Incremental BIST Generator Verification Design This design is similar to the PRBS BIST generator and verification design except the altgxb megafunction is configured to the incremental BIST mode Refer to the design for information on the ports and parameters required for altgxb in this mode...

Page 216: ...n outputcoreclk_out output tx_out outputrx_bisterr output rx_bistdone output rx_clkout output reset wire reset_wire wire VCC assign reset reset_wire assign VCC 1 Incr_BIST Incr_BIST_inst inclk inclk rx_in rx_in rx_slpbk VCC rxdigitalreset reset_wire inclk rx_in tx_out coreclk_out rx_clkout rx_bistdone rx_bisterr Incr_BIST tx_out 0 coreclk_out 0 rx_clkout 0 rx_bistdone 0 rx_bisterr 0 reset Incr_BIS...

Page 217: ...lk reset reset_wire endmodule Reset Module Design reset_mod v module reset_mod clk reset input clk output reset reg 19 0 counter reg reset always posedge clk counter counter 1 always counter begin if counter 20 b11111111111111100000 counter 20 b11111111111111111111 reset 1 b1 else reset 1 b0 end endmodule altgxb Instantiation Incr_BIST v module Incr_BIST inclk rx_in rx_slpbk rxdigitalreset tx_out ...

Page 218: ...done sub_wire3 0 0 wire 0 0 rx_bisterr sub_wire4 0 0 altgxb altgxb_component inclk inclk rx_in rx_in rx_slpbk rx_slpbk rxdigitalreset rxdigitalreset tx_out sub_wire0 coreclk_out sub_wire1 rx_clkout sub_wire2 rx_bistdone sub_wire3 rx_bisterr sub_wire4 defparam altgxb_component force_disparity_mode OFF altgxb_component channel_width 16 altgxb_component pll_inclock_period 6250 altgxb_component use_sy...

Page 219: ...n OFF altgxb_component intended_device_family Stratix GX altgxb_component use_equalizer_ctrl_signal OFF altgxb_component rx_enable_dc_coupling OFF altgxb_component run_length_enable OFF altgxb_component pll_use_dc_coupling OFF altgxb_component operation_mode DUPLEX altgxb_component use_8b_10b_mode ON altgxb_component use_rx_clkout ON altgxb_component data_rate_remainder 0 altgxb_component data_rat...

Page 220: ...hown The top level simply consists of calling the megafunction instance altgxb Instantiation High_Freq_BIST v module high_freq_BIST inclk tx_out coreclk_out input 0 0 inclk output 0 0 tx_out output 0 0 coreclk_out wire 0 0 sub_wire0 wire 0 0 sub_wire1 wire 0 0 tx_out sub_wire0 0 0 wire 0 0 coreclk_out sub_wire1 0 0 altgxb altgxb_component inclk inclk tx_out sub_wire0 coreclk_out sub_wire1 defparam...

Page 221: ...double_data_mode ON altgxb_component use_preemphasis_ctrl_signal OFF altgxb_component protocol CUSTOM altgxb_component clk_out_mode_reference ON altgxb_component preemphasis_ctrl_setting 0 altgxb_component use_channel_align OFF altgxb_component intended_device_family Stratix GX altgxb_component pll_use_dc_coupling OFF altgxb_component operation_mode TX altgxb_component use_8b_10b_mode ON altgxb_co...

Page 222: ...ion in the low frequency BIST mode Because this design consists only of a single transmitter design only the altgxb instantiation is shown The top level simply consists of calling the megafunction instance altgxb Instantiation low_freq_BIST v module low_freq_BIST inclk tx_out coreclk_out input 0 0 inclk output 0 0 tx_out output 0 0 coreclk_out wire 0 0 sub_wire0 wire 0 0 sub_wire1 wire 0 0 tx_out ...

Page 223: ...ponent use_vod_ctrl_signal OFF altgxb_component self_test_mode 3 altgxb_component use_double_data_mode ON altgxb_component use_preemphasis_ctrl_signal OFF altgxb_component protocol CUSTOM altgxb_component clk_out_mode_reference ON altgxb_component preemphasis_ctrl_setting 0 altgxb_component use_channel_align OFF altgxb_component intended_device_family Stratix GX altgxb_component pll_use_dc_couplin...

Page 224: ... altgxb megafunction in the mix frequency BIST mode Because this design consists only of a single transmitter design only the altgxb instantiation is shown The top level simply consists of calling the megafunction instance altgxb Instantiation mix_freq_BIST v module mix_freq_BIST inclk tx_out coreclk_out input 0 0 inclk output 0 0 tx_out output 0 0 coreclk_out wire 0 0 sub_wire0 wire 0 0 sub_wire1...

Page 225: ... use_vod_ctrl_signal OFF altgxb_component self_test_mode 4 altgxb_component use_double_data_mode ON altgxb_component use_preemphasis_ctrl_signal OFF altgxb_component protocol CUSTOM altgxb_component clk_out_mode_reference ON altgxb_component preemphasis_ctrl_setting 0 altgxb_component use_channel_align OFF altgxb_component intended_device_family Stratix GX altgxb_component pll_use_dc_coupling OFF ...

Page 226: ...8 22 Altera Corporation Stratix GX Transceiver User Guide January 2005 Design Examples Figure 8 9 Mix Frequency BIST Measured on tx_out ...

Page 227: ...x GX transceiver block has individual reset signals to reset the digital and analog portions of the channel The txdigitalreset rxdigitalreset and rxanalogreset signals affect the channels individually The pll_areset and pllenable signals affect the entire transceiver block The pll_areset signal is a power down signal and powers down the entire transceiver block The analog circuitry is powered down...

Page 228: ...f the transceiver block This signal is synchronized within the transceiver block The minimum duration required on the txdigitalreset signal is four parallel clock cycles f If you use REFCLKB pins in your design refer to Appendix C REFCLKB Pin Constraints for analog reset pll_areset rxanalogreset pll_enable refclkb usage constraints You do not have to use all of the reset and enable signals If the ...

Page 229: ...gnal in XAUI mode Table 9 1 Reset Signal Map to Stratix GX Blocks Transmitter Phase Compensation FIFO Module Byte Serializer Transmitter 8B 10B Encoder Transmitter Serializer Transmitter Analog Circuits Transmitter PLL Transmitter XAUI State Machine Transmitter Analog Circuits BIST Generators Receiver Deserializer Receiver Word Aligner Receiver Deskew FIFO Module Receiver Rate Matcher Receiver 8B ...

Page 230: ...eters and limitations You may want to add additional escape states and other system specific features in your design If your design requirements and GXB configurations are different for example usage for multiple transceivers from the design example you can make necessary changes using the flow chart and waveform figures in each section as guidelines Train Receive CRU With Transmit PLL Output Cloc...

Page 231: ...gh pll_areset low rxanalogreset high txdigitalreset high rxdigitalreset high pll_locked high waitstate_timer 0 pll_areset low rxanalogreset low txdigitalreset low rxdigitalreset high rx_freqlocked high pll_areset low rxanalogreset low txdigitalreset low rxdigitalreset low NO YES NO YES Start pll_areset low rxanalogreset low txdigitalreset low rxdigitalreset high wait_state NO YES transmit_digitalr...

Page 232: ...the receiver PLL After the CRU has transitioned to locking to data from locking to the reference clock the rx_freqlocked signal goes high which allows the CRU to transition into the wait state where a timer is loaded a certain amount of time See the Stratix GX FPGA Family data sheet for the amount of time loaded into the timer When the timer counts down rx_clkout is stable The reset controller the...

Page 233: ...reqlocked signal toggles the rxdigitalreset the receiver s digital circuit is reset However you can make changes to the design to avoid this if for example you want to debug your design without the core being reset If you plan to use REFCLKB pins in your design see Appendix C REFCLKB Pin Constraints for information about the effects of analog resets pll_arest rx_analogreset Copyright c Altera Corp...

Page 234: ... clock mode to lock to data mode input pll_locked Transmit PLL of GXB locked output rxdigitalreset GXB Receive digital reset output rxanalogreset Receive power down signal output txdigitalreset GXB transmit digital reset output pll_areset GXB power down signal reg rxdigitalreset wire rxanalogreset reg txdigitalreset reg pll_areset reg 2 0 state reg rxdigitalreset_inclk reg rxanalogreset_inclk reg ...

Page 235: ...1 b1 waitstate_timer WAITSTATE_TIMER_VALUE state STROBE_TXPLL_LOCKED end else begin rxdigitalreset_inclk 1 b0 rxanalogreset_inclk 1 b0 pll_areset 1 b0 state IDLE if transmit_digitalreset txdigitalreset 1 b1 else txdigitalreset 1 b0 end STROBE_TXPLL_LOCKED if sync_reset Synchronous Reset can be asserted in IDLE state After reset seq has finished begin rxdigitalreset_inclk 1 b1 rxanalogreset_inclk 1...

Page 236: ...eset 1 b0 end else begin state STABLE_TX_PLL rxdigitalreset_inclk 1 b1 rxanalogreset_inclk 1 b0 txdigitalreset 1 b0 pll_areset 1 b0 end WAIT_STATE if sync_reset Synchronous Reset can be asserted in IDLE state After reset seq has finished begin rxdigitalreset_inclk 1 b1 rxanalogreset_inclk 1 b1 txdigitalreset 1 b1 pll_areset 1 b1 state STROBE_TXPLL_LOCKED end else if rx_freqlocked Condition to have...

Page 237: ...talreset is only used for Receive GXB then synchronization is needed because internally the rxdigitalreset is only synchronized to recovered clock rx_clkout In the above description of the module a typical user likes to operate on the system clock or PLD clock domain To reset the rx_coreclk domain logic in PLD fabric following reset is useful rxanalogreset is optional because it is a power down si...

Page 238: ...igital resets must be at least four cycles long This design example does not cover all the digital reset scenarios in a system that resets the digital logic of the GXB In this example whenever the rx_freqlocked signal toggles the rxdigitalreset the receiver s digital circuit is reset However you can make changes to the design to avoid this if for example you want to debug your design without the c...

Page 239: ... rx_clkout Receive recovered clock input sync_reset Input synchronous reset from the system input async_reset Input async reset from system input transmit_digitalreset Input Reset only the transmit digital section input receive_digitalreset Input Reset the receiver section input rx_freqlocked rx_freqlocked signal from receive Transition from lock to reference clock mode to lock to data mode input ...

Page 240: ...set begin if async_reset begin rxdigitalreset_inclk 1 b1 rxanalogreset_inclk 1 b1 txdigitalreset 1 b1 pll_areset 1 b1 waitstate_timer WAITSTATE_TIMER_VALUE state STROBE_TXPLL_LOCKED end else case state IDLE if sync_reset Synchronous Reset can be asserted in IDLE state After reset seq has finished begin rxdigitalreset_inclk 1 b1 rxanalogreset_inclk 1 b1 txdigitalreset 1 b1 pll_areset 1 b1 waitstate...

Page 241: ...1 b1 txdigitalreset 1 b1 pll_areset 1 b0 end STABLE_TX_PLL if sync_reset Synchronous Reset can be asserted in IDLE state After reset seq has finished begin rxdigitalreset_inclk 1 b1 rxanalogreset_inclk 1 b1 txdigitalreset 1 b1 pll_areset 1 b1 state STROBE_TXPLL_LOCKED end else if rx_freqlocked begin state WAIT_STATE waitstate_timer waitstate_timer 1 b1 rxdigitalreset_inclk 1 b1 rxanalogreset_inclk...

Page 242: ... 1 b0 end else begin waitstate_timer waitstate_timer 1 b1 rxdigitalreset_inclk 1 b1 rxanalogreset_inclk 1 b0 txdigitalreset 1 b0 pll_areset 1 b0 state WAIT_STATE end end else begin rxdigitalreset_inclk 1 b1 rxanalogreset_inclk 1 b0 txdigitalreset 1 b0 pll_areset 1 b0 waitstate_timer WAITSTATE_TIMER_VALUE state STABLE_TX_PLL end default state IDLE endcase end synchronizing the rxdigitalreset to rec...

Page 243: ...italreset begin rxdigitalreset_rx_clkout_Q 1 b1 rxdigitalreset 1 b1 end else begin rxdigitalreset_rx_clkout_Q rxdigitalreset_inclk rxdigitalreset rxdigitalreset_rx_clkout_Q end end endmodule Train Receive CRU With Transmit PLL Output Clock Option Disabled The configuration in this section is similar to having two independent transmit and receive PLLs with their respective input reference clocks in...

Page 244: ...ption Figure 9 6 shows the transmitter reset sequence Transmit and Receive Duplex with Train RX CRU with TXPLL output clock option disabled Single Width 8 10 Double Width 16 20 rx_clkout rx_coreclk tx_coreclk inclk inclk tx_coreclk rx_clkout data path width Receive Parallel Clock Transmit Parallel Clock Receive Parallel Clock Transmit Parallel Clock ...

Page 245: ... the analog and digital portions of the transmitter and receiver After this signal is deasserted the controller waits until the transmitter PLL is stable pll_locked 1 b1 before deasserting tx_digitalreset This ensures that the output of the transmitter PLL is stable before releasing any of the logic that it feeds Start pll_areset high txdigitalreset high pll_areset low txdigitalreset high pll_lock...

Page 246: ...ransceiver User Guide January 2005 Recommended Resets Figure 9 7 Transmitter Reset Sequence Waveform Figure 9 8 shows the receiver reset sequence pll_areset tx_digitalreset pll_locked Output Status Reset Signals Stable TXPLL Clock 1 2 3 4 ...

Page 247: ...the value it signifies that rx_clkout is stable The reset controller then deasserts the rx_digital reset which completes the reset sequence You should be able to monitor the BER for example a synchronization state machine based on the Stratix GX transceiver data to determine whether the system is initialized and working properly f See the Stratix GX FPGA Family data sheet for the value of Trx_freq...

Page 248: ...wn in GXB terms and digital resets for transmit and receive All user input digital resets must be at least four cycles long This design example does not cover all the digital reset scenarios in a system that resets the digital logic of the GXB In this example whenever the rx_freqlocked signal toggles the rxdigitalreset the receiver s digital circuit is reset However you can make changes to the des...

Page 249: ...module reset_seq_tx_rx_rx_cruclk_rx_coreclk rx_coreclk inclk rx_cruclk sync_reset async_reset transmit_digitalreset receive_digitalreset pll_locked rx_freqlocked pll_areset txdigitalreset rxanalogreset rxdigitalreset input inclk GXB input reference clock input rx_cruclk Receive GXB input reference clock input rx_coreclk Receive recovered clock input sync_reset Input synchronous reset from the syst...

Page 250: ...3 b001 parameter STABLE_TX_PLL 3 b010 Parameter value of T 2ms based on the fastest clock or 3 1875 Gbps parameter WAITSTATE_TIMER_VALUE 1000000 reg 19 0 waitstate_timer timer for actual value refer stratix data sheet Transmit Reset Sequence always posedge inclk or posedge async_reset begin if async_reset begin txdigitalreset 1 b1 pll_areset 1 b1 state STROBE_TXPLL_LOCKED end else case state IDLE ...

Page 251: ...e begin state STROBE_TXPLL_LOCKED txdigitalreset 1 b1 pll_areset 1 b0 end STABLE_TX_PLL if sync_reset Synchronous Reset can be asserted in IDLE state After reset seq has finished begin txdigitalreset 1 b1 pll_areset 1 b1 state STROBE_TXPLL_LOCKED end else state IDLE default state IDLE endcase end Receive Reset Sequence always posedge rx_cruclk or posedge pll_areset if pll_areset begin rxanalogrese...

Page 252: ... rxdigitalreset to recovered clock domain If rxdigitalreset is used for Receive GXB then this synchronization is needed because internally the rxdigitalreset is only synchronized to recovered clock rx_clkout To reset the rx_coreclk domain logic in PLD fabric following reset is useful always posedge rx_coreclk or posedge async_reset if async_reset begin rxdigitalreset_rx_coreclk_Q 1 b1 rxdigitalres...

Page 253: ...eset scenarios in a system that resets the digital logic of the GXB In this example whenever the rx_freqlocked signal toggles the rxdigitalreset the receiver s digital circuit is reset However you can make changes to the design to avoid this if for example you want to debug your design without the core being reset If you plan to use REFCLKB pins in your design see Appendix C REFCLKB Pin Constraint...

Page 254: ..._reset Input async reset from system input transmit_digitalreset Input Reset only the transmit digital section input receive_digitalreset Input Reset the receiver section input rx_freqlocked rx_freqlocked signal from receive Transition from lock to reference clock mode to lock to data mode input pll_locked Transmit PLL of GXB locked output rxdigitalreset GXB Receive digital reset output rxanalogre...

Page 255: ...se case state IDLE if sync_reset Synchronous Reset can be asserted in IDLE state After reset seq has finished begin txdigitalreset 1 b1 pll_areset 1 b1 state STROBE_TXPLL_LOCKED end else begin pll_areset 1 b0 state IDLE if transmit_digitalreset txdigitalreset 1 b1 else txdigitalreset 1 b0 end STROBE_TXPLL_LOCKED if sync_reset Synchronous Reset can be asserted in IDLE state After reset seq has fini...

Page 256: ...DLE endcase end Receive Reset Sequence always posedge rx_cruclk or posedge pll_areset if pll_areset begin rxanalogreset 1 b1 rxdigitalreset_rx_cruclk 1 b1 waitstate_timer WAITSTATE_TIMER_VALUE end else begin if sync_reset begin rxanalogreset 1 b1 rxdigitalreset_rx_cruclk 1 b1 waitstate_timer WAITSTATE_TIMER_VALUE end else begin rxanalogreset 1 b0 if rx_freqlocked begin if waitstate_timer 0 begin w...

Page 257: ... of the module a typical designer likes to operate on the system clock or PLD clock domain where one would like to have a FIFO with rx_clkout domain being write clock and may have pld clock domain Generic name can be any clock name as read clock pld clock is optional To reset the rx_clkout domain logic in PLD fabric following reset is useful always posedge rx_clkout or posedge async_reset if async...

Page 258: ...t from the design example you can make necessary changes using the flow chart and waveform figures in each section as guidelines Receive CRU With Transmit PLL Output Clock Option Enabled This section provides some design examples that show a receive only configuration with train receive CRU and the transmit PLL output clock enabled Figure 9 10 shows the receive only clock options Figure 9 10 Recei...

Page 259: ...quence to transition into a wait state where a timer is loaded with T ms When the timer counts down the value it signifies that rx_clkout is stable The reset controller then deasserts the rx_digital reset which completes the reset sequence Start pll_areset high rxanologreset high rxdigitalreset high pll_areset low rxanalogreset low rxdigitalreset high rxfreqlocked high pll_areset low rxanalogreset...

Page 260: ...rates a sync_reset synchronous reset for the entire system The design example has an async_reset a power down in GXB terms and digital resets for transmit and receive All user input digital resets must be at least four cycles long This design example does not cover all the digital reset scenarios in a system that resets the digital logic of the GXB In this example whenever the rx_freqlocked signal...

Page 261: ... 8 10 bits or Double Width 16 20 bits receive parallel clock rx_coreclk Functional Mode Any RX PLL CRU Train RX PLL CRU with TX PLL ouput clock refClk as shown in Mega Wizard timescale 1ns 10ps module reset_seq_rx_ONLY_TXPLL_rx_coreclk rx_coreclk inclk sync_reset async_reset receive_digitalreset pll_locked rx_freqlocked pll_areset rxanalogreset rxdigitalreset input inclk GXB input reference clock ...

Page 262: ...r WAIT_STATE 3 b011 Parameter value of T 2ms based on the fastest clock or 3 1875 Gbps parameter WAITSTATE_TIMER_VALUE 1000000 reg 19 0 waitstate_timer timer for actual value refer stratix data sheet assign rxanalogreset rxanalogreset_inclk always posedge inclk or posedge async_reset begin if async_reset begin rxdigitalreset_inclk 1 b1 rxanalogreset_inclk 1 b1 pll_areset 1 b1 waitstate_timer WAITS...

Page 263: ...ock which is also fed to RX CRU else if pll_locked begin state STABLE_TX_PLL rxdigitalreset_inclk 1 b1 rxanalogreset_inclk 1 b0 pll_areset 1 b0 end else begin state STROBE_TXPLL_LOCKED rxdigitalreset_inclk 1 b1 rxanalogreset_inclk 1 b1 pll_areset 1 b0 end STABLE_TX_PLL if sync_reset Synchronous Reset can be asserted in IDLE state After reset seq has finished begin rxdigitalreset_inclk 1 b1 rxanalo...

Page 264: ...n Decrement a Timer of 2ms Refer Stratix GX Datasheet for accurate value after rx_freqlocked is asserted This time is given to ensure the recovered clock to be stable Cannot have any freq variations and is locked to incomming data if waitstate_timer 0 begin state IDLE rxdigitalreset_inclk 1 b0 rxanalogreset_inclk 1 b0 pll_areset 1 b0 end else begin waitstate_timer waitstate_timer 1 b1 rxdigitalres...

Page 265: ...xdigitalreset rxdigitalreset_rx_coreclk_Q end end endmodule Design Example 2 This design example shows a receive only configuration where inclk is the transmit PLL input reference clock the output of transmit PLL trains receive CRU and rx_clkout is the receive parallel interface clock This design example has the following constraints If your design requirements are different from the examples use ...

Page 266: ...era Corporation Contacting Altera We have made every effort to ensure that this design example works correctly If you have a question that is not answered by the information then please contact Altera Support Reset Sequence for the ALTGXB The configuration of GXB for which the following reset sequence is valid is Transmit and Receive Receiver ONLY Datapath Single Width 8 10 bits or Double Width 16...

Page 267: ... reg 2 0 state reg rxdigitalreset_inclk reg rxanalogreset_inclk reg rxdigitalreset_rx_clkout_Q reg rxanalogreset_rx_clkout_Q parameter IDLE 3 b000 parameter STROBE_TXPLL_LOCKED 3 b001 parameter STABLE_TX_PLL 3 b010 parameter WAIT_STATE 3 b011 Parameter value of T 2ms based on the fastest clock or 3 1875 Gbps parameter WAITSTATE_TIMER_VALUE 1000000 reg 19 0 waitstate_timer timer for actual value re...

Page 268: ...reset_inclk 1 b1 pll_areset 1 b1 state STROBE_TXPLL_LOCKED end Wait untill the TXPLL is locked to inclk and TX PLL has a stable output clock which is also fed to RX CRU else if pll_locked begin state STABLE_TX_PLL rxdigitalreset_inclk 1 b1 rxanalogreset_inclk 1 b0 pll_areset 1 b0 end else begin state STROBE_TXPLL_LOCKED rxdigitalreset_inclk 1 b1 rxanalogreset_inclk 1 b1 pll_areset 1 b0 end STABLE_...

Page 269: ...1 state STROBE_TXPLL_LOCKED end else if rx_freqlocked Condition to have rx_freqlocked signal a stable high and should not bounce around begin Decrement a Timer of 2ms Refer Stratix GX Datasheet for accurate value after rx_freqlocked is asserted This time is given to ensure the recovered clock to be stable Cannot have any freq variations and is locked to incomming data if waitstate_timer 0 begin st...

Page 270: ... domain generic name can be any clock name as read clock To reset the rx_clkout domain logic in PLD fabric following reset is useful always posedge rx_clkout or posedge async_reset if async_reset begin rxdigitalreset_rx_clkout_Q 1 b1 rxdigitalreset 1 b1 end else begin if receive_digitalreset begin rxdigitalreset_rx_clkout_Q 1 b1 rxdigitalreset 1 b1 end else begin rxdigitalreset_rx_clkout_Q rxdigit...

Page 271: ... flow charts and waveforms for each configuration as design guidelines The design example requires a reset controller that generates a sync_reset synchronous reset for the entire system The design example has an async_reset a power down in GXB terms and digital resets for transmit and receive All user input digital resets must be at least four cycles long This design example does not cover all the...

Page 272: ... for the ALTGXB The configuration of GXB for which the following reset sequence is valid is Transmit and Receive Receive Only Datapath Single Width 8 10 bits receive parallel clock rx_coreclk Functional Mode Any RX PLL CRU rx_cruclk timescale 1ns 10ps module reset_seq_rx_rx_cruclk_rx_coreclk rx_coreclk rx_cruclk sync_reset async_reset receive_digitalreset rx_freqlocked rxanalogreset rxdigitalreset...

Page 273: ...0000 reg 19 0 waitstate_timer timer for actual value refer stratix data sheet Receive Reset Sequence always posedge rx_cruclk or posedge async_reset if async_reset begin rxanalogreset 1 b1 rxdigitalreset_rx_cruclk 1 b1 waitstate_timer WAITSTATE_TIMER_VALUE end else begin if sync_reset begin rxanalogreset 1 b1 rxdigitalreset_rx_cruclk 1 b1 waitstate_timer WAITSTATE_TIMER_VALUE end else begin rxanal...

Page 274: ...ve GXB then this synchronization is needed because internally the rxdigitalreset is only synchronized to recovered clock rx_clkout To reset the rx_coreclk domain logic in PLD fabric following reset is useful always posedge rx_coreclk or posedge async_reset if async_reset begin rxdigitalreset_rx_coreclk_Q 1 b1 rxdigitalreset 1 b1 end else begin if receive_digitalreset begin rxdigitalreset_rx_corecl...

Page 275: ... that resets the digital logic of the GXB In this example whenever the rx_freqlocked signal toggles the rxdigitalreset the receiver s digital circuit is reset However you can make changes to the design to avoid this if for example you want to debug your design without the core being reset If you plan to use REFCLKB pins in your design see Appendix C REFCLKB Pin Constraints for information about th...

Page 276: ...the receiver section input rx_freqlocked rx_freqlocked signal from receive Transition from lock to reference clock mode to lock to data mode output rxdigitalreset GXB Receive digital reset output rxanalogreset Receive power down signal reg rxdigitalreset reg rxdigitalreset_rx_cruclk reg rxdigitalreset_rx_clkout_Q reg rxanalogreset Parameter value of T 2ms based on the fastest clock or 3 1875 Gbps ...

Page 277: ...k 1 b1 end end else begin rxdigitalreset_rx_cruclk 1 b1 waitstate_timer WAITSTATE_TIMER_VALUE end end end synchronizing the rxdigitalreset to recovered clock domain If rxdigitalreset is only used for Receive GXB then this synchronization is not needed because internally the rxdigitalreset is only synchronized to recovered clock rx_clkout In the above description of the module a designer likes to o...

Page 278: ...esign examples in this section show how to implement a reset sequence for the transmitter channels In this configuration GXB is configured only as a transmitter In the design examples the tx_coreclk option is not shown because the reset signals txdigitalreset based on tx_coreclk are synchronized internally by the reset controller in the Stratix GX hard IP This configuration only demonstrates the r...

Page 279: ...es a reset sequence Figure 9 15 Transmitter Reset Sequence Transmit ONLY Single Width 8 10 Double Width 16 20 tx_coreclk inclk tx_coreclk inclk Transmit Parallel Clock data path width Start pll_areset high txdigitalreset high pll_areset low txdigitalreset high pll_locked high pll_areset low txdigitalreset low transmit_digitalreset high pll_areset low txdigitalreset high YES NO YES NO async_reset o...

Page 280: ...ce clock and the transmit parallel interface clock This design example has the following constraints If your design requirements are different from the examples use the flow charts and waveforms for each configuration as design guidelines The design example requires a reset controller that generates a sync_reset synchronous reset for the entire system The design example has an async_reset a power ...

Page 281: ... is not answered by the information please contact Altera Support Reset Sequence for the ALTGXB The configuration of GXB for which the following reset sequence is valid is Transmit and Receive Transmit ONLY Datapath Single Width 8 10 bits or Double Width 16 20 bits Transmit parallel clock Functional Mode Any timescale 1ns 10ps module reset_seq_tx_ONLY inclk sync_reset async_reset transmit_digitalr...

Page 282: ...E_TXPLL_LOCKED end else case state IDLE if sync_reset Synchronous Reset can be asserted in IDLE state After reset seq has finished begin txdigitalreset 1 b1 pll_areset 1 b1 state STROBE_TXPLL_LOCKED end else begin pll_areset 1 b0 state IDLE if transmit_digitalreset txdigitalreset 1 b1 else txdigitalreset 1 b0 end STROBE_TXPLL_LOCKED if sync_reset Synchronous Reset can be asserted in IDLE state Aft...

Page 283: ...e the Stratix GX device All unused transceiver channels and transceiver blocks in a design are powered down to reduce the overall power consumption The power down feature cannot be used on the fly to turn the transceiver channels transceiver blocks on off without reconfiguration Table 9 2 details the state of the transceiver I O pins during power down Table 9 2 I O Pin States During Power Down Par...

Page 284: ...GND through a 10 kΩ resistor and connect refclkb to GXB_VCC through a 10 kΩ resistor to improve the device s immunity to noise 3 Altera recommends driving the reference resistor pin low for the powered down transceiver block 4 Transmitter output is tri stated at the lowest VOD setting and is toggling at any other setting However the VOD is 80 of the selected VOD setting 5 Receiver pin is pulled lo...

Page 285: ...des have two 10 bit equivalent codes associated with each 8 bit code The 10 bit codes can have either a neutral disparity or a non neutral disparity In the case of a neutral disparity 2 neutral disparity 10 bit codes are associated with an 8 bit code In the case of a non neutral disparity 10 bit code a positive and a negative disparity code are associated with the 8 bit code The positive disparity...

Page 286: ...ows if the conditions are not met then the running disparity at the end of the sub blocks are the same as the beginning of the sub block The current running disparity at the end of a sub block is positive if any of the following are true The sub block contains more ones than zeros The 6 bit sub block is 6 b000111 The 4 bit sub block is 4 b0011 The current running disparity at the end of a sub bloc...

Page 287: ...10_11100 10 b001111_0110 10 b110000_1001 K28 7 FC 8 b111_11100 10 b001111_1000 10 b110000_0111 K23 7 F7 8 b111_10111 10 b111010_1000 10 b000101_0111 K27 7 FB 8 b111_11011 10 b110110_1000 10 b001001_0111 K29 7 FD 8 b111_11101 10 b101110_1000 10 b010001_0111 K30 7 FE 8 b111_11110 10 b011110_1000 10 b100001_0111 Note to Table A 1 1 K28 5 is a comma code used for word alignment and indicates an IDLE s...

Page 288: ...000101 1011 D24 0 18 000 11000 110011 0100 001100 1011 D25 0 19 000 11001 100110 1011 100110 0100 D26 0 1A 000 11010 010110 1011 010110 0100 D27 0 1B 000 11011 110110 0100 001001 1011 D28 0 1C 000 11100 001110 1011 001110 0100 D29 0 1D 000 11101 101110 0100 010001 1011 D30 0 1E 000 11110 011110 0100 100001 1011 D31 0 1F 000 11111 101011 0100 010100 1011 D0 1 20 001 00000 100111 1001 011000 1001 D1...

Page 289: ...0 1001 D25 1 39 001 11001 100110 1001 100110 1001 D26 1 3A 001 11010 010110 1001 010110 1001 D27 1 3B 001 11011 110110 1001 001001 1001 D28 1 3C 001 11100 001110 1001 001110 1001 D29 1 3D 001 11101 101110 1001 010001 1001 D30 1 3E 001 11110 011110 1001 100001 1001 D31 1 3F 001 11111 101011 1001 010100 1001 D0 2 40 010 00000 100111 0101 011000 0101 D1 2 41 010 00001 011101 0101 100010 0101 D2 2 42 ...

Page 290: ... 100110 0101 D26 2 5A 010 11010 010110 0101 010110 0101 D27 2 5B 010 11011 110110 0101 001001 0101 D28 2 5C 010 11100 001110 0101 001110 0101 D29 2 5D 010 11101 101110 0101 010001 0101 D30 2 5E 010 11110 011110 0101 100001 0101 D31 2 5F 010 11111 101011 0101 010100 0101 D0 3 60 011 00000 100111 0011 011000 1100 D1 3 61 011 00001 011101 0011 100010 1100 D2 3 62 011 00010 101101 0011 010010 1100 D3 ...

Page 291: ...0 0011 D27 3 7B 011 11011 110110 0011 001001 1100 D28 3 7C 011 11100 001110 1100 001110 0011 D29 3 7D 011 11101 101110 0011 010001 1100 D30 3 7E 011 11110 011110 0011 100001 1100 D31 3 7F 011 11111 101011 0011 010100 1100 D0 4 80 100 00000 100111 0010 011000 1101 D1 4 81 100 00001 011101 0010 100010 1101 D2 4 82 100 00010 101101 0010 010010 1101 D3 4 83 100 00011 110001 1101 110001 0010 D4 4 84 10...

Page 292: ... 001001 1101 D28 4 9C 100 11100 001110 1101 001110 0010 D29 4 9D 100 11101 101110 0010 010001 1101 D30 4 9E 100 11110 011110 0010 100001 1101 D31 4 9F 100 11111 101011 0010 010100 1101 D0 5 A0 101 00000 100111 1010 011000 1010 D1 5 A1 101 00001 011101 1010 100010 1010 D2 5 A2 101 00010 101101 1010 010010 1010 D3 5 A3 101 00011 110001 1010 110001 1010 D4 5 A4 101 00100 110101 1010 001010 1010 D5 5 ...

Page 293: ...0 1010 D29 5 BD 101 11101 101110 1010 010001 1010 D30 5 BE 101 11110 011110 1010 100001 1010 D31 5 BF 101 11111 101011 1010 010100 1010 D0 6 C0 110 00000 100111 0110 011000 0110 D1 6 C1 110 00001 011101 0110 100010 0110 D2 6 C2 110 00010 101101 0110 010010 0110 D3 6 C3 110 00011 110001 0110 110001 0110 D4 6 C4 110 00100 110101 0110 001010 0110 D5 6 C5 110 00101 101001 0110 101001 0110 D6 6 C6 110 ...

Page 294: ... 010001 0110 D30 6 DE 110 11110 011110 0110 100001 0110 D31 6 DF 110 11111 101011 0110 010100 0110 D0 7 E0 111 00000 100111 0001 011000 1110 D1 7 E1 111 00001 011101 0001 100010 1110 D2 7 E2 111 00010 101101 0001 010010 1110 D3 7 E3 111 00011 110001 1110 110001 0001 D4 7 E4 111 00100 110101 0001 001010 1110 D5 7 E5 111 00101 101001 1110 101001 0001 D6 7 E6 111 00110 011001 1110 011001 0001 D7 7 E7...

Page 295: ...011010 1110 011010 0001 D23 7 F7 111 10111 111010 0001 000101 1110 D24 7 F8 111 11000 110011 0001 001100 1110 D25 7 F9 111 11001 100110 1110 100110 0001 D26 7 FA 111 11010 010110 1110 010110 0001 D27 7 FB 111 11011 110110 0001 001001 1110 D28 7 FC 111 11100 001110 1110 001110 0001 D29 7 FD 111 11101 101110 0001 010001 1110 D30 7 FE 111 11110 011110 0001 100001 1110 D31 7 FF 111 11111 101011 0001 0...

Page 296: ...A 12 Altera Corporation Stratix GX Transceiver User Guide January 2005 8B 10B Code ...

Page 297: ...efclkb pins see Appendix C REFCLKB Pin Constraints for information about analog reads and refclkb pin usage constraints Input port NUMBER_OF_QUADS 1 0 wide rx_in Yes Transceiver block receiver channel data input port Input port NUMBER_OF_CHANNELS 1 0 wide rx_cruclk No Clock recovery unit CRU for the transceiver block receiver PLL reference input clock Input port NUMBER_OF_QUADS 1 0 wide When you s...

Page 298: ...e serialfdbk port of the transceiver block receiver channel must be connected rx_a1a2size No Detects A1A2 or A1A1A2A2 input patterns If the signal is low 0 A1A2 patterns are detected If the signal is high 1 A1A1A2A2 patterns are detected Input port NUMBER_OF_CHANNELS 1 0 wide If you enable the rx_a1a2size port the PROTOCOL parameter must be set to SONET rx_equalizerctrl No Specifies the equalizer ...

Page 299: ...If you set the USE_8B_10B_MODE parameter to OFF and the USE_DOUBLE_DATA_MODE parameter is set to ON the deserialization factor is CHANNEL_WIDTH 2 If you set the USE_8B_10B_MODE parameter to ON the deserialization factor is 10 tx_ctrlenable No Control character enable Enables the 8B 10B encoder to identify control characters Labels an input character as a control code Input port NUMBER_OF_CHANNELS ...

Page 300: ...italreset No Sends a reset signal to the digital portion of the receiver Input port NUMBER_OF_QUADS 4 1 0 wide rxanalogreset No Sends a power down signal to the analog portion of the receiver Input port NUMBER_OF_QUADS 4 1 0 wide pllenable No Sends an enable signal to the transceiver block transmitter PLL Input port NUMBER_OF_QUADS 1 0 wide pll_areset No Sends a power down signal to the transceive...

Page 301: ...ardware which can take thousands of cycles for some settings coreclk_out No Output clock fed by the clk2 port of the transceiver block transmitter PLL Output port NUMBER_OF_QUADS 1 0 wide If a transceiver block transmitter PLL is used the coreclk_out port must be enabled rx_out Yes Transceiver block receiver PLL output data Output port CHANNEL_WIDTH NUMBER_OF_CHANNELS 1 0 wide If you set the USE_8...

Page 302: ...MODE parameter OFF the clock period must be doubled or the clock frequency must be halved rx_locked No Gives the status of the transceiver block receiver channel atom Output port NUMBER_OF_CHANNELS 1 0 wide Indicates that the transceiver block receiver PLL is locked to the reference input clock active low When the transceiver block receiver PLL is locked this signal is GND When the transceiver blo...

Page 303: ...ransceiver block receiver channel violated the value specified for the RUN_LENGTH parameter Output port NUMBER_OF_CHANNELS 1 0 wide rx_syncstatus No Provides the status of the pattern detector and word aligner Output port NUMBER_OF_CHANNELS DWIDTH_FACTOR 1 0 wide If you set the PROTOCOL parameter to XAUI or GigE the rx_syncstatus port is connected to the synchronization state machine and indicates...

Page 304: ...igE This signal is always set in the modes in which it is enabled It is still enabled even after the signal is a forced HIGH for backward compatibility with existing designs rx_bisterr No Error status signal for the self test Output port NUMBER_OF_CHANNELS 1 0 wide This port is available only if the USE_SELF_TEST_MODE parameter is turned on rx_bistdone No Indicates whether the self test is complet...

Page 305: ...eter is set to DUPLEX REVERSE_LOOPBACK _MODE String No Specifies the operation of the reverse loopback Values are NONE and RSLB If omitted the default is NONE Values other than NONE are available only when the OPERATION_MODE parameter is set to DUPLEX PROTOCOL String Yes Specifies the protocol Values are XAUI SONET GigE and Basic NUMBER_OF_CHANNELS Integer Yes Specifies the number of transceiver b...

Page 306: ... CHANNEL_WIDTH parameter value is 16 or 20 When the CHANNEL_WIDTH parameter value is 8 or 10 the transceiver block receiver channel is not in double data width mode Values are ON and OFF If omitted the default is OFF USE_8B_10B_MODE String No Specifies whether to use the 8B 10B decoder If this parameter is turned on the deserialization factor is 10 and the CHANNEL_WIDTH parameter value is 8 or 16 ...

Page 307: ...te alignment functions If this parameter is turned off the bit slipping operation is controlled by the rx_bitslip signal Values are ON and OFF If omitted the default is OFF USE_SYMBOL_ALIGN String No Specifies whether to use the word aligner Values are ON and OFF If omitted the default is ON ALIGN_PATTERN String No Specifies the pattern of 7 10 or 16 bits used by the word aligner for the USE_SYMBO...

Page 308: ...sceiver block receiver PLL or the transceiver block transmitter bandwidth type Values are LOW and HIGH If omitted the default is HIGH RX_BANDWIDTH_TYPE String No Specifies the transceiver block receiver PLL bandwidth type Values are LOW and HIGH If omitted the default is HIGH PLL_ENABLE_DC_ COUPLING String No Specifies whether to enable DC coupling on the transceiver block transmitter PLL clock in...

Page 309: ...ON and OFF If omitted the default is OFF If you enable this parameter the rx_cruclk port must be used RX_PPM_SETTING Integer No Specifies the value of the PPM threshold between the transceiver block receiver PLL VCO and the clock recovery unit CRU Values are 125 250 500 or 1000 If omitted the default is 1000 RX_FORCE_SIGNAL_ DETECT String No Specifies whether the rx_signaldetect port is used Value...

Page 310: ..._RATE Integer No Specifies in Mbps the rate of data from the GXB receiver channel If omitted the default is 0 RX_DATA_RATE_REMAINDER Integer No Specifies in bits per second bps the remainder of the RX_DATA_RATE parameter RX_DATA_RATE 1000000 This parameter helps to specify non integral data rates If omitted the default is 0 INTENDED_DEVICE_FAMILY String No Use this parameter for modeling and behav...

Page 311: ... also feeding the reset controller logic in the core logic The system may never come out of reset in this configuration Modeling in the Quartus II software simulation does not reveal this issue This issue also exists for multiple transceiver block applications that use the REFCLKB pin for clocking 2 Asserting the rxanalogreset signal of all four channels in a transceiver block resets its dedicated...

Page 312: ... PLL and affects the clock that feeds the core logic This behavior is not modeled in the Quartus II software simulation Figure C 1 shows an example of a problem configuration using the Stratix GX 25F device This configuration is also applicable to all devices in the Stratix GX device family Figure C 1 Example Configuration Stratix GX25F Device TX PLL TX PLL TX PLL TX PLL reset block reset block re...

Page 313: ...tical because the logic has enough time to recover during initialization Quartus II Software Version 4 0 For configurations 1 and 2 the Quartus II software version 4 0 prevents the sof file from being generated The assembler ASM will have an internal error IE Here are some of the messages from the Quartus II software log Internal Error Sub system ASM File asm_cdr cpp Line 839 Illegal Clock Placeme...

Page 314: ...for configurations 1 and 2 Error Can t place GXB pin HSDI_CLK1_IN_I at location AM7 because of incompatible location or I O standard assignments Error Can t place input clock HSDI_CLK1_IN_I at pin AM7 which is in the same quad as XGMII Error Can t place GXB transmitter or receiver channels and or their associated I O pins due to illegal location or I O standard assignments or inappropriate device ...

Page 315: ...t require that the PLLs be reset The PLLs have a wide pull in range and were able to relock to their respective reference clocks There might be situations where the read and write pointers in the phase compensation FIFO overlap This will manifest as incorrect transmit data and in some cases receive data A digital reset should correct this error Here are the reset and clocking recommendations Do no...

Page 316: ...s an example of a critical warning Figure C 3 Critical Warning The critical warning in this case warns you that the pll_areset signal will power down the clock pad Do not use the pll_areset pllenable or rxanalogreset signals in receive only configurations The Stratix GX device is used in various systems and configurations Based on the feedback and tests performed in the lab assertion of any or all...

Page 317: ...o the Stratix GX FPGA Family data sheet for more information on clocking resources available for each device in the family For designs that have receive only configurations try these solutions While asserting rxanalogreset ensure if possible that all four channels are not being reset at the same time Do not use the transmitter PLL train receive PLL from the receiver input reference clock rx_cruclk...

Page 318: ...C 8 Altera Corporation Stratix GX Transceiver User Guide January 2005 Known Issues ...

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