Altera Stratix GX, User Manual

Page: 257 / 318

Altera Corporation 9–31
January 2005 Stratix GX Transceiver User Guide
Reset Control & Power Down
rxdigitalreset_rx_cruclk <= 1'b1;
end
end
else
begin
rxdigitalreset_rx_cruclk <= 1'b1;
waitstate_timer <=
WAITSTATE_TIMER_VALUE;
end
end
end
/*synchronizing the rxdigitalreset to recovered clock domain
If rxdigitalreset is only used for Receive GXB, then the following
synchronization is not needed because
internally the rxdigitalreset is synchronized to recovered clock
(rx_clkout). In the above description
of the module, a typical designer likes to operate on the system
clock
or PLD clock domain where one would like to have a FIFO with
rx_clkout domain being write clock and
may have pld clock domain(Generic name, can be any clock name) as
read clock. pld clock is optional.
To reset the rx_clkout domain logic in PLD fabric following reset
is useful
*/
always @(posedge rx_clkout or posedge async_reset)
if(async_reset)
begin
rxdigitalreset_rx_clkout_Q <= 1'b1;
rxdigitalreset <= 1'b1;
end
else
begin
if(receive_digitalreset)
begin
rxdigitalreset_rx_clkout_Q <= 1'b1;
rxdigitalreset <= 1'b1;
end
else
begin
rxdigitalreset_rx_clkout_Q <=
rxdigitalreset_rx_cruclk;
rxdigitalreset <=
rxdigitalreset_rx_clkout_Q;
end
end
endmodule