Alpha Data ADM-XRC-7Z1, User Manual

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ADM-XRC-7Z1 User Manual
V2.6 - 14th February 2022
details on duplicating this VPD data.
Alternatively, FORCE2V5_L can be driven low to select 1.8V for the front I/O voltage. Note that FORCE2V5_L is
a signal name from a historical design, and the operating voltage will not be 2.5V but rather 1.8V if this mode is
used.
4.9.3 GTX Links
The PL has 8 GTX links to the P5 connector and 8 GTX lanes to the P6 connector (full pinout information for
these connectors are listed in Secondary XMC Connector, P5 and Secondary XMC Connector, P6 .
The 8 lanes to the P6 connector can be switched to connect to the XRM CN2 connector instead of the P6
connector, using SW1-6 and SW1-7. (See Table 4 )
The pin mappings are as follows:
Signal FPGA + Pin FPGA - Pin Rear Con Pin Rear Connector - Pin
P5_TX_0 N4 N3 P5.A1 P5.B1
P5_TX_1 P2 P1 P5.D1 P5.E1
P5_TX_2 R4 R3 P5.A3 P5.B3
P5_TX_3 T1 T1 P5.D3 P5.E3
P5_TX_4 V2 V1 P5.A5 P5.B5
P5_TX_5 W4 W3 P5.D5 P5.E5
P5_TX_6 Y1 Y2 P5.A7 P5.B7
P5_TX_7 AB2 AB1 P5.D7 P5.E7
- - - - -
P5_RX_0 P5 P6 P5.A11 P5.B11
P5_RX_1 T6 T5 P5.D11 P5.E11
P5_RX_2 U4 U3 P5.A13 P5.B13
P5_RX_3 V6 V5 P5.D13 P5.E13
P5_RX_4 AA4 AA3 P5.A15 P5.B15
P5_RX_5 Y6 Y5 P5.D15 P5.E15
P5_RX_6 AB6 AB5 P5.A17 P5.B17
P5_RX_7 AC4 AC3 P5.D17 P5.E17
Table 18 : PL RearMGT Mapping
Signal FPGA + Pin FPGA - Pin Rear Con Pin Rear Connector - Pin
P6_TX_0 AH2 AH1 P6.A1 P6.B1
P6_TX_1 AF2 AF1 P6.D1 P6.E1
P6_TX_2 AE4 AE3 P6.A3 P6.B3
P6_TX_3 AD2 AD1 P6.D3 P6.E3
P6_TX_4 AK10 AK9 P6.A5 P6.B5
P6_TX_5 AK6 AK5 P6.D5 P6.E5
Table 19 : PL RearMGT Mapping (continued on next page)
Page 17 Functional Description
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