Alpha Data ADM-XRC-7Z1, User Manual

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ADM-XRC-7Z1 User Manual
V2.6 - 14th February 2022
4.5 JTAG Interfaces
4.5.1 On-board Interface
By default, the 7Z1 is configured to have a single (cascaded) JTAG scan chain connected to header J4. This
allows the connection of the Xilinx JTAG cable for debug using the Xilinx ChipScope tools.
The board can also be set to have two independent scan chains using DIP switch SW2-3. (See Table 5 ). In
independent mode, the main chain (with the Zynq PL, CPLD and XRM interface) is connected to J4, while the
Zynq PS is connected to header J3.
If the cascaded or main scan chain is connected to the XMC connector (when SW1-5 is ON), header J4 should
not be used.
4.5.2 XMC Interface
The JTAG interface on the XMC connector is normally unused and XMC_TDI connected directly to XMC_TDO.
The interface can be connected to the cascaded or main interface (through level-translators) by switching SW1-5
ON. See Table 4
4.5.3 JTAG Voltages
The on-board JTAG scan chains uses 1.8V. The Vcc supply provided on J3 and J4 to the JTAG cable is +1.8V
and is protected by a poly fuse rated at 350mA. 3.3V signals must not be used at header J3 or J4.
The JTAG signals at the XMC interface use 3.3V signals and are connected through level translators to the
on-board scan chain.
The JTAG signals at the XRM2 interface use the adjustable voltage XRM_VIO.
4.6 Clocks
The board has nine reference clocks: two from the carrier, and seven generated on-board.
The clocks MGTCLK250M, PROGCLK, REFCLK200M and ETH_CLK25M are generated by a single Silicon
Labs Si5338B and are all synchronous.
Note:
Clock Termination
The LVDS clocks do not have termination resistors on the circuit board. On-die terminations in the FPGA must
be enabled by setting the attribute "DIFF_TERM = TRUE". This can either be set in the source code when
instantiating the buffer, or in the design constraints file.
4.6.1 PCIe Reference Clock (PCIEREFCLK)
The 100MHz PCI Express reference clock is provided by the carrier card through the Primary XMC connector,
P5, at pins A19 and B19. This is connected to the Zynq PL via 10nF AC coupling capacitors. On the Zynq PL, it
is connected to GTX Quad 112 to allow its use as reference for the eight GTX lanes on Quads 111 and 112.
Page 10 Functional Description
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