Alpha Data ADM-XRC-7Z1, User Manual

Page: 17 / 36

ADM-XRC-7Z1 User Manual
V2.6 - 14th February 2022
Signal Target FPGA Input IO Standard "P" pin "N" pin
PCIEREFCLK MGTREFCLK0_112 HSCL N8 N7
Table 8 : PCIEREFCLK Connections
4.6.2 P6 Reference Clock (P6REFCLK)
A reference clock can be provided by the carrier card through the Secondary XMC connector, P6, at pins A19
and B19. This is connected to the Zynq PL via 10nF AC coupling capacitors. On the Zynq PL, it is connected to
GTX Quad 109 to allow its use as reference for the eight GTX lanes on Quads 109 and 110.
Signal Target FPGA Input IO Standard "P" pin "N" pin
P6REFCLK MGTREFCLK0_109 LVDS or HSCL AD10 AD9
Table 9 : P6REFCLK Connections
4.6.3 MGTCLK250M
The fixed 250.0MHz reference clock, MGTCLK250M, is a differential clock signal using LVDS. Two phase
matched copies are MGTREFCLK inputs on the Zynq PL at GTX Quad 109 and 111. Since each input can clock
the adjacent GTX Quads, this clock can be used by all GTX links on the board.
Signal Target FPGA Input IO Standard "P" pin "N" pin
MGTCLK250M_A MGTREFCLK0_111 LVDS_25 U8 U7
MGTCLK250M_B MGTREFCLK1_109 LVDS_25 AF10 AF9
Table 10 : MGTCLK250M Connections
4.6.4 PROGCLK
The programmable clock, PROGCLK, is a differential clock signal using LVDS. It is connected to MGTREFCLK
inputs on the Zynq PL at GTX Quad 110. Since this input can clock the adjacent GTX Quads, it can be used by
the GTX links on quads 109 and 111.
Signal Target FPGA Input IO Standard "P" pin "N" pin
PROGCLK MGTREFCLK1_110 LVDS_25 AC8 AC7
Table 11 : PROGCLK Connections
Page 11 Functional Description
ad-ug-1253_v2_6.pdf