ADM-PCIE-9V5 User Manual
2.2 Chassis Requirements
2.2.1 PCI Express
The ADM-PCIE-9V5 is capable of PCIe Gen 3 with 8 lanes, using the Xilinx Integrated Block for PCI Express.
2.2.2 Mechanical Requirements
An 8 or 16 lane physical PCIe slot is required for mechanical compatibility.
2.2.3 Power Requirements
The ADM-PCIE-9V5 draws power from the PCIe Edge and the 6-pin ATX power connector. The ADM-PCIE-9V5
does not use or require the 3.3V power from the PCIe Edge (though it does use 3.3V AUX). Revision 1 cards
(serial number less than 110) require both PCIe edge and 6-pin ATX power connector. Revision 2 and onward
can operate with only the PCIe edge. As per PCIe specification, using only the PCIe edge with this configuration
limits the power consumption of the card to a maximum 66W. Adding the 6-pin ATX connector provides additional
75W of power, bringing the total board power dissipation maximum to 141W.
Power consumption estimation requires the use of the Xilinx XPE spreadsheet and a power estimator tool
available from Alpha Data. Please contact [email protected] to obtain this tool.
The power available to the rails calculated using XPE are as follows:
Voltage
Source Name
Current Capability
0.85-0.90
V VCC VCC_BRAM
80A
0.9
MGTAVCC
8A
1.2
MGTAVTT
15A
1.8
VCC VCCO_1.8V
3A
1.8
MGTVCCAUX
1A
3.3
3.3V for Optics
9A
Table 2 : Available Power By Rail
Page 3
Board Information
ad-ug-1385_v1_0.pdf
