ADM-PCIE-9V5 User Manual
when system resets and power cycles are not an option.
The Alpha Data System Monitor is also capable of reconfiguring the flash memory and reprograming the FPGA.
This provides a useful failsafe mechanism to re-program the FPGA even if it drops off the PCIe bus. The system
monitor can be accessed with avr2util over USB at the front panel and rear edge.
3.8.1.1 Building and Programming Configuration Images
Generate a bitfile with these constraints (see xapp1233):
•
set_property BITSTREAM.GENERAL.COMPRESS TRUE [ current_design ]
•
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
•
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
•
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design]
•
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
•
set_property BITSTREAM.CONFIG.UNUSEDPIN {Pullnone} [current_design]
•
set_property CFGBVS GND [ current_design ]
•
set_property CONFIG_VOLTAGE 1.8 [ current_design ]
•
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
Generate an MCS file with these properties (write_cfgmem):
•
-format MCS
•
-size 256
•
-interface SPIx8
•
-loadbit "up 0x0000000 <directory/to/file/filename.bit>" (0th location)
Program with vivado hardware manager with these settings (see xapp1233):
•
SPI part: mt25qu01g-spi-x1_x2_x4_x8
•
State of non-config mem I/O pins: Pull-none
3.8.2 Configuration via JTAG
A micro-USB AB Cable may be attached to the front panel or rear edge USB port. This permits the FPGA to be
reconfigured using the Xilinx Vivado Hardware Manager via the integrated Digilent JTAG converter box. The
device will be automatically recognized in Vivado Hardware Manager.
For more detailed instructions, please see “Using a Vivado Hardware Manager to Program an FPGA Device”
section of Xilinx UG908: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/
ug908-vivado-programming-debugging.pdf
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Functional Description
ad-ug-1385_v1_0.pdf
