Alinx ZYNQ7000 FPGA, User Manual, Page: 34 / 46

ZYNQ FPGA Development Board AX7350B User Manual
34 / 46
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ZYNQ
U1
BANK112
GTX
收发器
PCIex8 卡槽
PCIE_TX1_P/N
PCIE_TX0_P/N
PCIE_RX3_P/N
PCIE_RX2_P/N
PCIE_PRSNT
PCIE_TX2_P/N
PCIE_TX3_P/N
PCIE_RX1_P/N
PCIE_RX0_P/N
PCIE_PERST
LEVEL
SHIFT
PCIE_PRSNT_LS
PCIE_PERST_LS
SI5338P
Figure 12-1: PCIe slot design schematic
PCIe x4 Interface Pin Assignment
：
Signal Name FPGA Pin Description
PCIE_RX0_P AB4 PCIE Channel 0 Data Receive Positive
PCIE_RX0_N AB3 PCIE Channel 0 Data Receive Negative
PCIE_RX1_P Y4 PCIE Channel 1 Data Receive Positive
PCIE_RX1_N Y3 PCIE Channel 1 Data Receive Negative
PCIE_RX2_P V4 PCIE Channel 2 Data Receive Positive
PCIE_RX2_N V3 PCIE Channel 2 Data Receive Negative
PCIE_RX3_P T4 PCIE Channel 3 Data Receive Positive
PCIE_RX3_N T3 PCIE Channel 3 Data Receive Negative
PCIE_TX0_P AA2 PCIE Channel 0 Data Transmit Positive
PCIE_TX0_N AA1 PCIE Channel 0 Data Transmit Negative
PCIE_TX1_P W2 PCIE Channel 1 Data Transmit Positive
PCIE_TX1_N W1 PCIE Channel 1 Data Transmit Negative
PCIE_TX2_P U2 PCIE Channel 2 Data Transmit Positive
PCIE_TX2_N U1 PCIE Channel 2 Data Transmit Negative
PCIE_TX3_P R2 PCIE Channel 3 Data Transmit Positive