ZYNQ FPGA Development Board AX7350B User Manual
26 / 46
Amazon Store: https://www.amazon.com/alinx
Table 8-1: PHY chip default configuration value
When the network is connected to Gigabit Ethernet, the data
transmission of ZYNQ and PHY chip JL2121 is communicated through the
RGMII bus, the transmission clock is 125Mhz, and the data is sampled on the
rising edge and falling samples of the clock.
When the network is connected to 100M Ethernet, the data transmission of
ZYNQ and PHY chip JL2121 is communicated through RMII bus, and the
transmission clock is 25Mhz. Data is sampled on the rising edge and falling
samples of the clock. Figure 8-1 detailed the connection of the ZYNQ PS end 1
way Ethernet PHY chip, and Figure 8-2 detailed the connection of the 1 way
Ethernet PHY chip on the ZYNQ PL side:
ZYNQ
GPHY
(JL2121)
PHY1_TXCK
U169
U1
BANK
501
PHY1_TXCTL
PHY1_TXD0~PHY1_TXD3
PHY1_RXCK
PHY1_RXCTL
PHY1_TXD0~PHY1_RXD3
PHY1_MDC
PHY1_MDIO
BANK
500
PHY1_RESET
Figure 8-1: The connection of the ZYNQ PS end and GPHY chip