Alinx ZYNQ7000 FPGA, User Manual, Page: 33 / 46

ZYNQ FPGA Development Board AX7350B User Manual
33 / 46
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SFP1_TX_DIS_LS AA14 SFP Module Transmission Prohibition
High Level Active
SFP1_LOSS_LS W16 SFP Receives LOSS signal, High Indicates No
optical signal received
The Second fiber interface ZYNQ pin assignment is as follows:
Signal Name ZYNQ Pin Description
SFP2_TX_P
AE2 SFP Module Data Transmission Positive
SFP2_TX_N AE1 SFP Module Data Transmission Negative
SFP2_RX_P AC6 SFP Module Data Receive Positive
SFP2_RX_P
AC5 SFP Module Data Receive Negative
SFP2_TX_DIS_LS Y16 SFP Module Transmission Prohibition
High Level Active
SFP2_LOSS_LS W15 SFP Receives LOSS signal, High Indicates No
optical signal received
Part 12: PCIe Slot
The AX7350B FPGA development board has a PCIe x8 slot that physically
connects to the PCIe board. In the electrical connection, we only have 4 pairs
of transceivers connected to the PCIEx8 slot, so only PCIEex4, PCIex2,
PCIex1 data communication can be realized.
The transmit and receive signals of the PCIe interface are directly
connected to the GTX transceiver of the ZYNQ BANK112. The four TX signals
and the RX signals are connected to the BANK112 by differential signals, and
the single-channel communication rate can be up to 5G bit bandwidth. The
reference clock of the PCIe slot is provided by the clock chip SI5338P with a
reference clock frequency of 100Mhz.
The PCIe interface design diagram of the FPGA development board is
shown in Figure 12-1, where the TX transmission signal is connected in AC
coupling mode.