ZYNQ FPGA Development Board AX7350B User Manual
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PL Clock Pin Assignment:
Signal Name
ZYNQ
Pin
CLK0_P
C8
CLK0_N
C7
Transceiver Reference Clock
One 156mhz differential crystal oscillator is provided to bank111 as the
reference clock of SPF of GTX transceiver; In addition, two channels of
100MHz differential reference clock are generated by the dsc557-0334fi1 chip
and provided to the bank112 and PCIe socket respectively. The schematic
diagram of the reference circuit design is shown in the following figure:
156.25M
hz
ZYNQ
CLOCK
DSC557-0334FI1
U51
U1
BANK
111
PCIE_CLK0_P/N
SFP_CLK0_P/N
PCIE_REFCLK_P/N
BANK
112
PCIE
插槽
CLK0+
CLK0-
CLK1+
CLK1-
P1
Figure 6-4 Programmable clock source
Programmable clock source ZYNQ pin assignment:
：
Signal Name
ZYNQ
Pin