AKM AKD4114-B, Manual

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[AKD4114-B]
[KM076604] 2009/08 - 3 -
a-3. Set-up of AK4114 input path
It sets up by SW 1_1 and SW 1_5 in parallel mode. Please set up IPS2-0 bits in serial mode.
-
IPS1 pin
(SW1_5)
IPS0 pin
(SW1_1)
IPS2 bit IPS1 bit IPS0 bit
INPUT Data
0 0 0 RX0 Default
0 0 1 RX1
0 1 0 RX2
0 1 1 RX3
1 0 0 RX4
1 0 1 RX5
1 1 0 RX6
1 1 1 RX7
(In parallel mode, IPS2 is fixed to “0”)
Table 3. Recovery Data Select
b. Set-up of clock input and output
The signal level outputted/inputted from PORT2 is 3.3V.
PORT2
DIR
5
6
1
10
GND GND GND GND GND
MCL
K
BI
C
K
LRCK SDTO DAU
X
Figure 2. PORT2 pin layout
b-1. MCKO1/MCKO2
The output of MCKO1 pin or MCKO2 pin can be selected by JP12. The output frequency of
MCKO1/MCKO2 is selected by OCKS 1-0.
Output
signal
JP12
MCKO1 MCKO1
Default
MCKO2 MCKO2
Table 4. Set-up of MCKO1/MCKO2
OCKS1 pin
(SW3_2)
OCKS0 pin
(SW3_3)
OCKS1 bit OCKS0 bit
(X’tal) MCKO1 MCKO2 fs (max)
0 0 256fs 256fs 256fs 96 kHz
Default
0 1 256fs 256fs 128fs 96 kHz
1 0 512fs 512fs 256fs 48 kHz
1 1 128fs 128fs 64fs 192 kHz
Table 5. Master Clock Frequency Select