Agilent Technologies E1445A, User'S Manual And Scpi Programming Manual

Page: 437 / 534

The Operation
Status Group
The Operation Status Group monitors current operating conditions within
the AFG. The specific conditions include: calibrating, sweeping, entering
the wait-for-arm state, and execution of the
INITiate:IMMediate command.
The Condition Register
Calibration, sweeping, waiting for an arm signal, and the
INITiate:IMMediate
command are monitored with the following bits in the Condition Register. All
other bits are unused.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
unused INIT ARM unused SWE unused CAL
–
CALibrating: Bit 0 is set (1) during calibration. The bit is cleared
(0) otherwise.
–
SWEeping: Bit 3 is set (1) while a frequency sweep or list is in
progress. The bit is cleared (0) when waveform generation is halted,
when frequency sweeping or lists are not selected, and at the end of
each sweep or list.
–
Waiting for ARM: Bit 6 is set (1) when the AFG enters the
wait-for-arm state. The bit is cleared (0) when a start arm is
received or when waveform generation is aborted.
–
INITiated: Bit 8 is set (1) when the INITiate:IMMediate command is
executed. The bit is cleared (0) when waveform generation is
complete and the AFG returns to the Idle state.
Reading the Condition Register
Bit settings in the Condition Register can be determined with the command:
STATus:OPERation:CONDition?
Bits 0, 3, 6, and 8 have corresponding decimal values of 1, 8, 64, and 256.
Reading the Condition Register does not affect the bit settings. The bits are
cleared following a reset (
*RST ).
The Transition Filter
The Transition Filter specifies which type of bit transition in the Condition
Register will set corresponding bits in the Event Register. Transition filter bits
may be set for positive transitions ( 0 to 1), or negative transitions (1 to 0). The
commands used to set the transitions are:
STATus:OPERation:NTRansition < unmask >
STATus:OPERation:PTRansition <
unmask
>
NTRansition sets the negative transition. For each bit unmasked, a 1 to 0
transition of that bit in the Condition Register sets the associated bit in the
Event Register.
Chapter 9 AFG Status 435