Agilent Technologies E1406A, User'S Manual And Scpi Programming Manual

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Transition Filter
The Transition Filter specifies which types of bit state changes in the
Condition Register will set corresponding bits in the Event Register.
Transition Filter bits may be set for positive transitions (PTR), negative
transitions (NTR), or both. Positive means a condition bit changes from 0
to 1. Negative means a condition bit changes from 1 to 0. Transition Filters
are read-write, and are unaffected by
*CLS (clear status) or queries. They
are set to instrument-dependent values at power on and after *RST (reset).
If there are no commands to access a particular Transition Filter, it has a
fixed setting. This setting is specified in the instrument’s programming
guide or command dictionary. Most of our VXI instruments assign the
Transition Filter to detect positive transitions only.
Event Register
The Event Register latches transition events from the Condition Register as
specified by the Transition Filter. Bits in the Event Register are latched,
and, once set, they remain set until cleared by a query or
*CLS (clear status).
There is no buffering; so while an event bit is set, subsequent events
corresponding to that bit are ignored. Event Registers are read-only.
Enable Register
The Enable Register specifies which bits in the Event Register can
generate a summary bit. The instrument logically ANDs corresponding bits
in the Event and Enable Registers, and ORs all the resulting bits to obtain a
summary bit. Summary bits are, in turn, recorded in another register, often
the Status Byte. Enable Registers are read-write, and are not affected by
*CLS (clear status). Querying Enable Registers does not affect them. There
is always a command to read and write to the Enable Register of a particular
status group.
An Example Sequence
Figure 4-4 illustrates the response of a single bit position in a typical status
group for various settings. The changing state of the condition in question
is shown at the bottom of the figure. A small binary table shows the state of
the chosen bit in each Status Register at the selected times T1 – T5.
Figure 4-4. Typical Status Bit Changes in a Status Register
Chapter 4 Triggering and System Status 105