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Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer
The Sampling Tab
State Acquisition Modes
100 MHz / 128K State
All pods are available. Memory depth is 128 K samples per
channel
. If
time or state
count
is turned on in
Trigger Settings
, the total memory
is split between data acquisition storage and time or state count
storage. To maintain the full memory depth of 128 K samples per
channel, leave one pod pair unassigned. (To unassign a pod pair, select
the
Pod Assignment
button under the
Format
tab; then, drag a pod
pair to unassigned.) State clock speed matches your target system's
clock, up to 100 MHz.
Timing Acquisition Modes
In conventional timing acquisition mode the analyzer stores
measurement data at each sampling interval.
128K Sample Full Channel 250MHz Max
The total memory depth is 128 K samples per
channel
, with data being
sampled and stored as often as every 4 ns. You can set the sample rate
to go slower with the Sample Period control.
256K Sample Half Channel 500MHz
Only one pod of each pod pair is available. Channels assigned to
unavailable pods are ignored. You can specify which pod to use by
toggling the
Pod
field. The total memory depth is 256K samples per
channel
. Data is sampled and stored every 2 ns; this rate cannot be
changed.
See Also
“Sample Period (Timing Only)” on page 46
“Pod Selection” on page 69
Transitional Timing Acquisition Modes
In transitional timing modes, the timing analyzer samples data at
regular intervals just like it does in conventional timing mode.
However, in transitional timing mode, it only stores data when there is
a change on the lines assigned to a label within a pod pair.
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