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Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer
Specifications and Characteristics
Minimum Master-to-Master Clock Time:* 10.0 ns
Setup/Hold Time:*
Single Clock, Single Edge: 0.0/4.0 ns through 4.0/0.0 ns,
adjustable in 500-ps increments
Single Clock, Multiple Edge: 0.0/4.5 ns through 4.5/0.0 ns,
adjustable in 500-ps increments
Multiple Clock, Multiple Edge: 0.0/5.0 ns through 5.0/0.0 ns,
adjustable in 500-ps increments
* Specified for an input signal VH=-0.9 V, VL=-1.7 V, threshold=-1.3 V,
slew rate=1 V/ns
Agilent Technologies 16712A Logic Analyzer
Characteristics
The characteristics are not specifications, but are included as
additional information.
General information
- Channel Counts:
1-card module 96 data, 6 clock
2-card module 198 data, 6 clock
- Memory Depth: Full Channel Half Channel
16710A 8 Ksamples 16 Ksamples
16711A 32 Ksamples 64 Ksamples
16712A 128 Ksamples 256 Ksamples
Probes
- Input Resistance: 100 Kohm, +/- 2%
- Parasitic tip capacitance: 1.5 pF
- Minimum Voltage Swing: 500 mV peak-to-peak
- Maximum Voltage: +/- 40 V peak, CAT I
- Threshold Range: +/- 6.0 V, adjustable in 50-mV increments
State Analysis
- Maximum State Clock Speed 100 MHz
- Minimum State Clock Pulse Width: 3.5 ns**
- Minimum Slave-to-Slave Clock Time 10.0 ns**
- Minimum Master-to-Slave Clock Time 0.0 ns**
- Minimum Slave-to-Master Clock Time 4.0 ns**
- State Clocks: 6
- State Clock Qualifiers: 4
Each qualifier can be set to
recognize one of six clock
lines, either high or low.
- State Clock Qualifier Setup/Hold 4.0/0.0 ns, not adjustable
- Time Tag Resolution: 8 ns
- Maximum Time Count Between States: 34.3 seconds
- Maximum State Tag Count: 4.29e9
- Context Store Block Sizes 16/32/64 states
** Minimum times are given for an input signal
VH=-0.9 V, VL=-1.7 V, threshold=-1.3 V, slew rate=1 V/ns
Timing Analysis
- Maximum Conventional Timing Rate:
Half Channel 500 MHz
Full Channel 250 MHz
- Maximum Transitional Timing Rate:
Full Channel 125 MHz
- Sample Period Accuracy: 0.01% of sample period
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