Advantech SOM-ETX Design Guide
Table 5.7 PCI Clock Signals Routing Summary
Trace
Impedance
PCI Routing Requirements
Topology
Maximum trace
Length
Damping
Resistor
55 Ohm
10%
6 mils width, 50 mils spacing (based on
stackup ssumptions)
2~4
Devices
W1:0.5 inch
W2:5 inch
W3(a,b,c,d):15 inch
W4:0.5 inch
W5:as long as need
R1: 33
ohm
R2: 33
ohm
Note:
Clocks skew between PCI slots/devices should be less than 2ns@33MHz and
1ns@66MHz. The recommend value of the clock trace tolerance of W3(a,b,c,d) is 5
inch(Max).
5.1.4 Application Notes
5.1.4.1 REQ/GNT
These signals are used only by bus-mastering PCI devices. Most SOM-ETX modules
do not have enough REQ/GNT pairs available to support a bus-mastering device at
every slot position. A PCI arbiter design is recommended when extra REQ/GNT pairs
are required. Figure 5.5 show the example design for PCI arbiter :
33
FRAME#
1
STOP#
2
SYSREQ#
3
SYSGNT#
4
PCIREQ1#
5
VSS
6
PCIGNT1#
7
PCIREQ2#
8
VCC
9
PCIGNT2#
10
PCIREQ3#
11
PCIGNT3#
12
VC3A
13
VC5A
14
AVCC
28
PCICLKI
27
RESET#
26
AVSS
25
VSS
24
PCICLK0
23
PCICLK1
22
VCC
21
PCICLK2
20
PCICLK3
19
PCICLK4
18
VSS
17
VC3B
16
VC5B
15
MS-1
33
33
33
33
MS1PCICLK
PCIRST#
PCIREQ#1
STOP#
FRAME#
MS1PREQ#1
PCIGNT#1
MS1PREQ#3
MS1PGNT#2
MS1PREQ#2
MS1PGNT#3
MS1PGNT#1
PCICLK1
PCICLK2
PCICLK3
Figure 5-5 Design Example PCI Arbiter
If there are less than four REQ/GNT pairs available for external devices, they will be
assigned starting with the REQ0#/GNT0# pair. Therefore, external bus-mastering
devices should be placed in the lowest numbered slot positions and non-bus
mastering devices should be placed in the highest-numbered slot positions. Refer to
Chapter 2.X.X REQ/GNT for the details
Chapter 5 Carrier Board Design Guidelines
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