Advantech SOM-ETX Design Guide
Chapter 4 General Design Recommendations
A brief description of the Printed Circuit Board (PCB) for SOM-ETX based boards is
provided in this section. From a cost- effectiveness point of view, a four-layer board is
the target platform for the motherboard design. For better quality, a six-layer or 8-
layer board is preferred.
4.1 Nominal Board Stack-Up
The trace impedance typically noted (55
Ω
± 10%) is the “nominal” trace impedance
for a 5-mil wide external trace and a 4-mil wide internal trace. However, some stack-
ups may lead to narrower or wider traces on internal or external layers in order to
meet the 55-
Ω
impedance target, that is, the impedance of the trace when not
subjected to the fields created by changing current in neighboring traces. Note the
trace impedance target assumes that the trace is not subjected to the EMI fields
created by changing current in neighboring traces.
It is important to consider the minimum and maximum impedance of a trace based on
the switching of neighboring traces when calculating flight times. Using wider spaces
between the traces can minimize this trace-to-trace coupling. In addition, these wider
spaces reduce settling time.
Coupling between two traces is a function of the coupled length, the distance
separating the traces, the signal edge rate, and the degree of mutual capacitance
and inductance. In order to minimize the effects of trace-to-trace coupling, the routing
guidelines documented in this Section should be followed. Also, all high speed,
impedance controlled signals should have continuous GND referenced planes and
cannot be routed over or under power/GND plane splits.
Chapter 4 General Design Recommendations
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