Advantech SOM-ETX Design Guide
Chapter 5 Carrier Board Design Guidelines
5.1 PCI-Bus
SOM-ETX provides a PCI Bus interface that is compliant with the PCI Local Bus
Specification, Revision 2.2. The implementation is optimized for high-performance
data streaming when SOM-ETX is acting as either the target or the initiator on the
PCI bus. For more information on the PCI Bus interface, refer to the PCI Local Bus
Specification, Revision 2.2.
5.1.1 Signal Description
Table 5.1 shows SOM-ETX PCI bus signal, including pin number, signals, I/0, and
descriptions.
Table 5.1 PCI Signal Description
Pin Signal
I/O
Description
A7,8,3,4 PCICLK[1..4] I PCI clock outputs for up to 4 external PCI slots or devices.
A22,15,1
3,9
PCIREQ[0..3] I
Bus Request signals for up to 4 external bus mastering PCI
devices. When asserted, it means a PCI device is requesting
PCI bus ownership from the arbiter.
GNT[0..3] O
Grant signals to PCI Masters. When asserted by the arbiter,
the PCI master has been granted ownership of the PCI bus.
- AD[0..31] I/O
PCI Address and Data Bus Lines. These lines carry the
address and data information for PCI transactions.
A31,49,7
0,82
CBE[0..3] I/O
PCI Bus Command and Byte Enables. Bus command and
byte enables are multiplexed in these lines for address and
data phases, respectively.
A53 PAR
I/O
Parity bit for the PCI bus.
A54 SERR#
OD
System Error. Asserted for hardware error conditions such
as parity errors detected in DRAM.
A55 PERR#
I/O
Parity Error. For PCI operation per exception granted by PCI
2.1 Specification.
A57 PME#
OD
Power management event.
A59
LOCK#
I/O
Lock Resource Signal. This pin indicates that either the PCI
master or the bridge intends to run exclusive transfers.
A60
DEVSEL#
I/O
Device Select. When the target device has decoded the
address as its own cycle, it will assert DEVSEL#.
A61
TRDY#
I/O
Target Ready. This pin indicates that the target is ready to
complete the current data phase of a transaction.
A63
IRDY#
I/O
Initiator Ready. This signal indicates that the initiator is ready
to complete the current data phase of a transaction.
A64
STOP#
I/O
Stop. This signal indicates that the target is requesting that
the master stop the current transaction.
A65
FRAME#
I/O
Cycle Frame of PCI Buses. This indicates the beginning and
duration of a PCI access.
A93
PCIRST#
I
PCI Bus Reset. This is an output signal to reset the entire
PCI Bus. This signal is asserted during system reset.
A97,98,9
5,96
INT[A.D] OD
PCI interrupts from CPU-PCI bridge.
A17,14,1
1,10
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