Appendix B
Block Diagram ................................................ 35
Appendix C
Register Structure and Format .................... 37
C.1 Overview ............................................................................ 37
C.2 I/O Port Address Map ........................................................ 37
C.3 Channel Number and A/D Data — BASE+0 and
BASE+1 .............................................................................. 42
C.4 Software A/D Trigger — BASE+0 .................................... 42
C.5 A/D Channel Range Setting — BASE+2 ......................... 43
C.6 MUX Control — BASE+4 and BASE+5 ............................ 44
C.7 Status Register — BASE+6 and BASE+7 ......................... 45
C.8 Control Register — BASE+6 ............................................. 46
C.9 Clear Interrupt and FIFO — BASE+8 and BASE+9 ......... 47
C.10 D/A Output Channel 0 — BASE+10 and BASE+11 ......... 47
C.11 D/A Output Channel 1 — BASE+12 and BASE+13 ......... 48
C.12 D/A Reference Control —BASE+14 ................................ 49
C.13 Digital I/O Registers — BASE+16 and BASE+17 ............ 50
C.14 Programmable Timer/Counter Registers BASE+24,
BASE+26, BASE+28 and BASE+30 ................................. 50
Appendix D
82C54 Counter Function ............................... 51
D.1 The Intel 82C54 .................................................................. 51
D.2 Counter Read/Write and Control Registers ..................... 51
D.3 Counter Operating Modes ................................................ 53
D.4 Counter Operations ........................................................... 55
