APPENDIX C
PCI-1711/1731 User’s Manual
Advantech Co., Ltd.
www.advantech.com
– 44 –
Write
MUX Control
Bit #
7
6
5
4
3
2
1
0
BASE+5
CH3
CH2
CH1
CH0
BASE+4
CL3
CL2
CL1
CL0
C.6 MUX Control — BASE+4 and BASE+5
Table C-5 Register for multiplexer control
CL3 ~ CL0
Start Scan Channel Number
CH3 ~ CH0
Stop Scan Channel Number
l
When you set the gain code of analog input channel n, you should
set the MUX start&stop channel number to channel n to prevent
any unexpected errors. In fact BASE+4 bit 3 to bit 0, CL3 ~ CL0, act
as a pointer to channel n’s address in the SRAM when you program
the A/D channel setting (refer to Section C.5).
Caution!
We recommend you set the same start and stop channel when writing
to the register BASE+2. Otherwise, if the A/D trigger source is on, the
multiplexer will continuously scan between channels and the range
setting may be set to an unexpected channel. Make sure the A/D
trigger source is turned off to avoid this kind of error.
The write-only registers of BASE +4 and BASE+5 control how the
multiplexers (MUXs) scan.
l
BASE+4 bit 3 to bit 0, CL3 ~ CL0, hold the start scan channel num-
ber.
l
BASE+5 bit 3 to bit 0, CH3 ~ CH0, hold the stop scan channel num-
ber.
Writing to these two registers automatically initializes the scan range
of the MUXs. Each A/D conversion trigger also sets the MUXs to the
next channel. With continuous triggering, the MUXs will scan from
the start channel to the stop channel and then repeat. The following
examples show the scan sequences of the MUXs.
Example 1
If the start scan input channel is AI3 and the stop scan input channel
is AI7, then the scan sequence is AI3, AI4, AI5, AI6, AI7, AI3, AI4,
AI5, AI6, AI7, AI3, AI4…
