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Q7-AL

BIOS Checkpoints, Beep Codes

Status Code

Description

0x10

System is waking up from the S1 sleep state

0x20

System is waking up from the S2 sleep state

0x30

System is waking up from the S3 sleep state

0x40

System is waking up from the S4 sleep state

0xAC

System has transitioned into ACPI mode. Interrupt controller is in PIC mode.

0xAA

System has transitioned into ACPI mode. Interrupt controller is in APIC mode.

8.3. OEM-Reserved Checkpoint Ranges

Status Code

Description

0x05

OEM SEC initialization before microcode loading

0x0A

OEM SEC initialization after microcode loading

0x1D – 0x2A

OEM pre-memory initialization codes

0x3F – 0x4E

OEM PEI post memory initialization codes

0x80 – 0x8F

OEM DXE initialization codes

0xC0 – 0xCF

OEM BDS initialization codes

Summary of Contents for Q7-AL

Page 1: ...Q7 AL User s Manual Qseven Computer On Module COM with Embedded Intel Atom Pentium and Celeron Processors Manual Rev 1 0 Revision Date March 2 2018 Part Number 50 1Z231 1000...

Page 2: ...damages Environmental Responsibility ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union s Restriction of Hazardou...

Page 3: ...18 2 12 Operating Temperatures 19 2 13 Environmental 19 2 14 Specification Compliance 19 2 15 Operating Systems 19 2 16 Functional Diagram 20 2 17 Mechanical Drawing 21 2 18 Q7 AL Heatspreaders 22 2...

Page 4: ...Configuration Space Map 44 6 6 PCI Interrupt Routing Map 46 6 7 SMBus Address Table 46 7 BIOS Setup 47 7 1 Menu Structure 47 7 2 Main 48 7 3 Advanced 50 7 4 Chipset 60 7 5 Security 66 7 6 Boot 67 8 B...

Page 5: ...4 Q7 AL HS2 Heat Spreader Mechanical Drawing 23 Figure 5 Q7 AL HS4 Passive Heatsink Mechanical Drawing 24 Figure 6 Q7 AL HS5 Passive Heatsink Mechanical Drawing 25 Figure 7 Q7 AL Connector Switch and...

Page 6: ...Definition on the Qseven Module 31 Table 3 40 pin Debug Connector Pin Definition on the Qseven Module 32 Table 4 LED Descriptions 34 Table 5 BIOS Select and Mode Configuration Switch Settings 35 Tabl...

Page 7: ...these two generations of SoCs New Intel SoC features Integrated heat spreader on Atom E3950 E3940 and E3930 Extended temperature SKUs 40 C to 85 C Windows 10 IOT support Gen 9 graphics engine with 18...

Page 8: ...2 Introduction This page intentionally left blank...

Page 9: ...m N4200 Quad Core 6W TDP 1 1 GHz base freq 2 5 GHz burst freq up to 2400 MT s 200MHz graphics base freq 750MHz graphics burst freq Celeron N3350 Dual Core 6W TDP 1 1 GHz base freq 2 4 GHz burst freq u...

Page 10: ...heduler 2 0 1 0 XPDM support DirectX 12 OpenGL 4 3 OpenGL ES 3 0 and OpenCL 2 0 Multi Display Support 3 independent displays Note Availability of features may vary between processor SKUs Display Types...

Page 11: ...ntegrated Intel HD Audio integrated on SoC Codec Located on carrier Q7 BASE ALC886 standard support 2 5 LAN Integrated MAC integrated on SoC Intel PHY Intel Ethernet Controller I210 IT or I211 IT Inte...

Page 12: ...USB 6 7 and 6x USB 2 0 ports USB 0 1 2 3 4 5 1x client and 5x Host All USBs supported by XHCI controller SATA 2x SATA 6Gb s ports 1x used for optional SATA SSD GPIO 8 GPIO from BMC multiplexed with LP...

Page 13: ...pport up to 115 2k bps Console Redirection selectable in BIOS supported during BIOS POST 2 8 SEMA Board Controller Type ADLINK Smart Embedded Management Agent SEMA Functions Voltage Current monitoring...

Page 14: ...0 Pentium SoC 6W N3350 Celeron SoC Input Type Regulated DC Voltage Regulated DC Voltage Regulated DC Voltage Regulated DC Voltage Regulated DC Voltage Typical Idle Mode Current and Power EIST enabled...

Page 15: ...umidity Operating 5 90 RH non condensing Storage 5 95 RH and operating with conformal coating Shock and Vibration IEC 60068 2 64 and IEC 60068 2 27 MIL STD 202F Method 213B Table 213 I Condition A and...

Page 16: ...20 Specifications 2 16 Functional Diagram Figure 1 Q7 AL Functional Block Diagram...

Page 17: ...Q7 AL Specifications 21 2 17 Mechanical Drawing All are dimensions shown in millimeters Tolerances should be 0 25mm unless otherwise noted Figure 2 Q7 AL Mechanical Drawing...

Page 18: ...or N series The heat spreaders must be combined with additional forms of cooling such as active heatsinks The Q7 AL HS3 active heatsink must be combined with one of the two heat spreaders Q7 AL HS1 or...

Page 19: ...e lower profile SoCs As can be seen in Figure 1 the Intel Pentium and Celeron N4200 N3350 SoCs come without mounted Intel heat spreaders and their profiles are 2mm lower than the Atom E39xx SoCs See t...

Page 20: ...om E39xx SoCs come with mounted Intel heat spreaders which look like metallic lids and add 2mm to the heights of the SoCs The Q7 AL HS 4 passive heatsink is designed for the extra heights of these SoC...

Page 21: ...lower profile SoCs As can be seen in Figure 1 the Intel Pentium and Celeron N4200 N3350 SoCs come without mounted Intel heat spreaders and their profiles are 2mm lower than the Atom E39xx SoCs See th...

Page 22: ...26 Specifications 2 19 Q7 AL Top View and Bottom View...

Page 23: ...ignal PU PD Pin Signal PU PD 1 GND 2 GND 3 GBE_MDI3 4 GBE_MDI2 5 GBE_MDI3 6 GBE_MDI2 7 GBE_LINK100 8 GBE_LINK1000 9 GBE_MDI1 10 GBE_MDI0 11 GBE_MDI1 12 GBE_MDI0 13 GBE_LINK 14 GBE_ACT 15 GBE_CTREF 16...

Page 24: ...X0 77 U3_USB1_TX_P USB_P7 USB_SST X0 78 U3_USB1_RX_P USB_P6 USB_SSR X0 79 USB_OC1 USB_6_7_OC 80 USB_OC1 USB_4_5_OC 81 U2_USB4_N USB_P5 USB_SSTX2 82 U2_USB5_N USB_P4 USB_SSRX1 83 U2_USB4_P USB_P5 USB_S...

Page 25: ..._BKLT_E N LVDS_BLEN 113 eDP0_TX3 LVDS_A3 LVDS Default PU 470k V1P8S 114 DDI0_TX3 eDP1_TX3 LVDS_B3 LVDS Default 115 eDP0_TX3 LVDS_A3 LVDS Default PU 470k V1P8S 116 DDI0_TX3 eDP1_TX3 LVDS_B3 LVDS Defaul...

Page 26: ...157 PCIE_CLK_REF 158 PCIE_RST 159 GND 160 GND 161 PCIE3_TX 162 PCIE3_RX 163 PCIE3_TX 164 PCIE3_RX 165 GND 166 GND 167 PCIE2_TX 168 PCIE2_RX 169 PCIE2_TX 170 PCIE2_RX 171 UART0_TX 172 UART0_RTS 173 PC...

Page 27: ...SPI_SCK 204 MFG_NC4 205 VCC_5V_SB 206 VCC_5V_SB 207 MFG_NC0 208 MFG_NC2 209 MFG_NC1 210 MFG_NC3 211 NC 212 NC 213 NC 214 NC 215 NC 216 NC 217 NC 218 NC 219 VCC 220 VCC 221 VCC 222 VCC 223 VCC 224 VCC...

Page 28: ...Output 5V signal level I O 3 3V Bi directional signal 3 3V tolerant I O 5V Bi directional signal 5V tolerant I O 3 3Vsb Input 3 3V tolerant active in standby state P Power Input Output REF Reference v...

Page 29: ...hernet Controller 0 activity indicator active low O 3 3VSB max 10 mA GBE0_LINK 13 Gigabit Ethernet Controller 0 link indicator active low O 3 3VSB max 10 mA GBE0_LINK100 7 Gigabit Ethernet Controller...

Page 30: ...0K 3 3V SDIO_PWR 47 SDIO Power Enable This signal is used to enable the power being supplied to a SD MMC card device O CMOS 3 3V PU 100K 3 3V SDIO_DAT0 3 48 DAT1 49 DAT0 50 DAT3 51 DAT2 SDIO Data line...

Page 31: ...iator the speaker in PC AT systems When not in use for this primary purpose it can be used as General Purpose PWM Output O CMOS 3 3V PU 10K 3 3V BIOS_DISABLE BOOT_ALT 41 Module BIOS disable input sign...

Page 32: ...N 77 75 USB transmit differential pair for superspeed USB 3 0 port 1 O USB 3 0 compliant AC coupled on module U3_USB1_RX_P U3_USB1_RX_N 78 80 USB receive differential pair for superspeed USB 3 0 port...

Page 33: ...3V LVDS_3P3_BKLT_EN 112 LVDS panel backlight enable O 3 3V LVDS_3P3_BKLT_CTRL 123 LVDS panel backlight brightness control O 3 3V ePD to LVDS requirement 3P3_LVDS_DDC_CLK 127 DDC lines used for flat pa...

Page 34: ...gnal Pin Description I O PU PD Comment TMDS_CLK TMDS_CLK 131 133 DDI1 differential pair for HDMI clock O eDP DP AC coupled on module TMDS_LANE1 TMDS_LANE1 137 139 DDI1 differential pair for HDMI lane...

Page 35: ...PCIE AC coupled close to respective device PCIE3_TX PCIE3_TX 161 163 PCI Express channel 3 Transmit Output differential pair O PCIE PCIe port 3 is used by LAN by default Build option supports PCIe po...

Page 36: ...e termination of a broken cycle I O CMOS 3 3V LPC_LDRQ 192 LPC serial DMA request signal I O CMOS 3 3V LPC_SERIRQ 191 LPC serial interrupt signal I O CMOS 3 3V 3 3 14 SPI Signal Pin Description I O PU...

Page 37: ...Reset button input This input may be driven active low by an external circuitry to reset the Qseven module I CMOS 3 3V PU 4 7K 3 3V suspend LID_BTN 22 LID button Low active signal used by the ACPI op...

Page 38: ...s active the system immediately transitions to the S5 State Soft Off O CMOS 3 3V 3 3 18 Fan Control Management Signal Pin Description I O PU PD Comment BMC_ PWM_OUT 196 Primary functionality is fan sp...

Page 39: ...Debug Module The DB40 debug board can be connected via a FPC 40 pin flat cable to the module It provides bus extensions to the SPI bus out of band BIOS flashing and the BMC access to Board Management...

Page 40: ...30 Connector Pinouts on Module Figure 8 Q7 AL and the DB40 Debug Module 4 3 36 pin MIPI CSI2 Camera Connector FPC Connector Type Flatfoil with 0 5mm pitch Pin Orientation...

Page 41: ...CMOS 1 8V OD output 19 CN_I2C_CAM0_DAT Camera 0 Control Interface Data I2C like interface CMOS 1 8V OD input output 20 CAM0_ENA Camera 0 Enable active low CMOS 1 8V output 21 CAM_MCLK_R Master Clock...

Page 42: ...Signal 1 NC RESERVED 2 SMC Debug SMC_STATUS 3 BIOS_MODE 4 SEL_BIOS 5 POSTWDT_DIS 6 Test Point SUS_S5 7 SUS_S4 8 SUS_S3 9 CB_PWROK 10 CB_RESET 11 SYS_RESET 12 PWRBTN 13 SMC Program Interface SMC_OCD0B...

Page 43: ...IOS_CLK 35 SPI_BIOS_MOSI 36 SPI_BIOS_MISO 37 SPI_BIOS_CS1 38 SPI_BIOS_CS0 39 GND 40 VCC_SPI_IN SPI power input from flash tool to module Note The pin definition on the debug module is the inverse of t...

Page 44: ...e 3Vcc S0 LED ON S3 S5 LED OFF ECO mode LED OFF During normal operation this LED is switched on LED3 Red BMC output and same signal as WDT 72 on BtB connector This LED indicates the watchdog timer act...

Page 45: ...on the carrier In dual BIOS Failsafe mode both BIOS chips on the module are configured as SPI1 Only one of the two is connected to the SPI bus at any given time In case of failure of the primary SPI1...

Page 46: ...36 Connector Pinouts on Module This page intentionally left blank...

Page 47: ...d maximum temperature values of CPU and board are stored in flash Power cycles counter Boot counter Counts the number of boot attempts Watchdog Timer Set Reset Disable Watchdog Timer Features auto rel...

Page 48: ...3 V1P8_A MSB 8 LSB x 3 3 1024 15 Q7 MSB 8 LSB x 1 826 x 3 3 1024 16 MAIN CURRENT Use Main Current Function 5 1 2 Main Current The BMC of the Q7 AL implements a current monitor The current can be read...

Page 49: ...eption Codes Exception Code Error Message 0 NOERROR 2 NO_SUSCLK 3 NO_SLP_S4_S5 4 NO_SLP_S3 5 BIOS_FAIL 6 RESET_FAIL 7 RESETIN_FAIL 8 NO_VIN_PWR_BAD 9 CRITICAL_TEMP 10 POWER_FAIL 11 VOLTAGE_FAIL 12 NO_...

Page 50: ...40 Smart Embedded Management Agent SEMA This page intentionally left blank...

Page 51: ...S Compatibility Memory 6 2 Direct Memory Access Channels Channel Number Data Width System Resource 0 8 bits Generic 1 8 bits Generic 2 8 bits Generic 3 8 bits Generic 4 Reserved cascade channel 5 16 b...

Page 52: ...Controller 80h LPC eSPI or PCIe 84h 86h Reserved 88h Reserved 8Ch 8Eh Reserved 90h Alias to 80h 092 Reset Generator 94h 96h Aliases to 8xh 98h Alias to 88h 9Ch 9Eh Alias to 8xh A0h A1h Interrupt Cont...

Page 53: ...RIRQ PIRQ Note 1 13 GSPI UART I2C SDIO N A Note 1 14 Gpio PIRQ Note 1 15 Gpio PIRQ Note 1 Note 1 These IRQs can be used for PCI devices when onboard device is disabled APIC Mode IRQ Typical Interrupt...

Page 54: ...ce 31 Function 0 LPC Interface eSPI Enable Strap 0 eSPI Interface eSPI Enable Strap 1 Bus 0 Device 31 Function 1 P2SB Bus 0 Device 31 Function 2 PMC Bus 0 Device 31 Function 3 Intel High Definition Au...

Page 55: ...troller Bus 0 Device 22 Function 0 Intel MEI 1 Bus 0 Device 22 Function 1 Intel MEI 2 Bus 0 Device 22 Function 2 IDE Redirection IDE R Bus 0 Device 22 Function 3 Keyboard and Text KT Redirection Bus 0...

Page 56: ...PCIE port1 PCIE port 2 PCIE port 3 PCIE port 4 PCIE port5 Int0 INTA 16 INTA 16 INTB 17 INTC 18 INTD 19 INTA 16 Int1 INTB 17 INTC 18 INTD 19 INTA 16 INTB 17 Int2 INTC 18 INTD 19 INTA 16 INTB 17 INTC 18...

Page 57: ...umn of the respective table Main Advanced Chipset Security Boot Save Exit BIOS Information System Information Board Information System Date System Time CPU Configuration Graphics Configuration Power M...

Page 58: ...ata Info only Data and Time MRC Version Info only Intel MRC Version GOP Version Info only Intel GOP Version TXE FW Version Info only Intel TXE FW Version BIOS Boot Source Info only Display Platform Cu...

Page 59: ...time in seconds the system is running in S0 state This counter is cleared when the system is removed from the external power supply Power Cycles Read only The returned value specifies the number of t...

Page 60: ...e the PROCHOT will be driven If bi direction is enabled external agents can drive PROCHOT to throttle the processor Thermal Monitor Disabled Enabled Enable Disable Thermal Monitor Monitor Mwait Disabl...

Page 61: ...en enabled CPU will switch to minimum speed when all cores enter C State Max Package C State PC2 PC1 C0 Controls the Max Package C State that the processor will Support Max Core C State Fused Value Co...

Page 62: ...based on silicon default support value 7 3 2 Advanced Graphics Configuration Feature Options Description LVDS Info only Data format and Color Depth VESA 24 bpp JEIDA 24 bpp JEIDA VESA 18 bpp Data form...

Page 63: ...ke OS show shutdown message during system shutdown Lock Legacy Resources Disabled Enabled Enables or Disables Lock of Legacy Resources LID Function Disabled Enabled Enables or Disables LID function EC...

Page 64: ...orted Features Info only Uptime Power Cycles Counter Info only System Reset Event Info only 1024 Bytes User Flash Info only Watchdog Info only Temperatures Info only Voltage Monitor Info only Display...

Page 65: ...out value for Control Bulk and Interrupt transfers 7 3 5 1 Advanced Thermal Management Temperatures and Fan Speed Feature Options Description Temperatures and Fan Info only CPU Temperature Info only...

Page 66: ...ways UPON REQUEST GA20 can be disabled using BIOS services ALWAYS do not allow disabling GA20 this option is useful when any RT code is executed above 1MB Boot option filter UEFI and Legacy Legacy onl...

Page 67: ...Both computers should have the same or compatible settings COM 2 Info only Console Redirection Disabled Enabled Console Redirection enable or disable Console Redirection Settings Submenu The settings...

Page 68: ...OS Redirection 80x24 80x25 On legacy OSes the number of rows and columns supported by redirection Putty KeyPad VT100 LINUX XTERMR6 SCO ESCN VT400 Select Function Key and KeyPad on Putty Redirection A...

Page 69: ...roller Disabled Enabled Enable Disable onboard Intel I210LM LAN Controller Network Stack Disabled Enabled Enable Disable UEFI Network Stack 7 3 12 Advanced Miscellaneous Feature Options Description Sm...

Page 70: ...d Only Display Memory Slot3 information Max TOLUD 2 GB 2 25 GB 2 5 GB 2 75 GB 3 GB Maximum Value of TOLUD Above 4GB MMIO BIOS assignment Disable Enable Enable Disable above 4GB memory mapped IO BIOS a...

Page 71: ...36 Select LFP panel used by Internal Graphics Device by selecting the appropriate setup item GOP Brightness level Value Set GOP Brightness Level1 Value ranges from 0 255 7 4 3 2 Chipset Uncore Configu...

Page 72: ...tures 7 4 4 1 Chipset South Cluster Configuration HD Audio Configuration Feature Options Description HD Audio Configuration Info only HD Audio Support Disabled Enabled Enable Disable HD Audio Support...

Page 73: ...PCI Express Configuration PCIe Express Root Port 1 4 Feature Options Description PCIe Express Root Port 1 4 Disabled Enabled Control the PCI Express Root Port Auto To disable unused root port automati...

Page 74: ...PCIE LTR Disabled Enabled PCH PCIE Latency Reporting Enable Disable Snoop Latency Override Disable Manual Auto Snoop Latency Override for PCH PCIE Disable Disable override Manual Manually enter overri...

Page 75: ...port has a Mechanical Preserve Switch Note Requires hardware support Spin Up Device Enabled Disabled If enabled for any ports Staggered Spin Up will be performed and only the drives which have this op...

Page 76: ...t South Cluster Configuration Miscellaneous Feature Options Description State After G3 S0 State S5 State Last State Specify what state to go to when power is re applied after a power failure G3 State...

Page 77: ...te Quiet Boot Disabled Enabled Enable or disables Quiet Boot option Fast Boot Disabled Enabled Enable or Disable Fast Boot features Most probes are skipped to reduce time cost during boot New Boot Opt...

Page 78: ...68 BIOS Setup This page intentionally left blank...

Page 79: ...Platform Innovation Framework for EFI the Framework The Framework refers to the following boot phases which may apply to various status code checkpoint descriptions Security SEC initial low level ini...

Page 80: ...overy errors PEI 8 2 Standard Status Codes 8 2 1 SEC Phase Status Code Description 0x00 Not used Progress Codes 0x01 Power on Reset type detection soft hard 0x02 AP initialization before microcode loa...

Page 81: ...ridge initialization North Bridge module specific 0x19 Pre memory South Bridge initialization is started 0x1A Pre memory South Bridge initialization South Bridge module specific 0x1B Pre memory South...

Page 82: ...ge module specific 0x3F 0x4E OEM post memory initialization codes 0x4F DXE IPL is started PEI Error Codes 0x50 Memory initialization error Invalid memory type or incompatible memory speed 0x51 Memory...

Page 83: ...ss started 0xF3 Recovery firmware image is found 0xF4 Recovery firmware image is loaded 0xF5 0xF7 Reserved for future AMI progress codes Recovery Error Codes 0xF8 Recovery PPI is not available 0xF9 Re...

Page 84: ...ecific 0x6E North Bridge DXE initialization North Bridge module specific 0x6F North Bridge DXE initialization North Bridge module specific 0x70 South Bridge DXE initialization is started 0x71 South Br...

Page 85: ...IDE Enable 0xA4 SCSI initialization is started 0xA5 SCSI Reset 0xA6 SCSI Detect 0xA7 SCSI Enable 0xA8 Setup Verifying Password 0xA9 Start of Setup 0xAA Reserved for ASL see ASL Status Codes section b...

Page 86: ...rror loading Boot Option LoadImage returned error 0xDA Boot Option is failed StartImage returned error 0xDB Flash update is failed 0xDC Reset protocol is not available 8 2 6 DXE Beep Codes of Beeps De...

Page 87: ...itioned into ACPI mode Interrupt controller is in PIC mode 0xAA System has transitioned into ACPI mode Interrupt controller is in APIC mode 8 3 OEM Reserved Checkpoint Ranges Status Code Description 0...

Page 88: ...78 BIOS Checkpoints Beep Codes This page intentionally left blank...

Page 89: ...onnector is designed for ultra low power CPUs and chipsets with ultra low Thermal Design Power TDP Refer to the following illustration for the mechanical dimensions of the Qseven edge connector NOTE T...

Page 90: ...a thermal solution for a specific Qseven module and can have a fan or be fanless depending on the thermal requirements 9 2 3 Installation Install a heat spreader or passive heat sink using the follow...

Page 91: ...ive components on the module and the mounting holes on the heat spreader or heatsink line up with the mounting holes on the module See the following two photos Step 5 Insert the Qseven module with mou...

Page 92: ...crews provided to fasten the heat spreader or four 2 7mm panhead screws to fasten the passive heatsink to the module Refer to the following four photos Install the screws using an alternating installa...

Page 93: ...ing to the carrier board In Top mounting the threaded standoffs are on the carrier board and the thermal solution is equipped with through hole standoffs For mounting dimension requirements refer to t...

Page 94: ...To avoid electrical shock and or damage to equipment Keep equipment away from water or liquid sources Keep equipment away from high heat or high humidity Keep equipment properly ventilated do not bloc...

Page 95: ...0 0200 Toll Free 1 800 966 5200 USA only Fax 1 408 360 0222 Email info adlinktech com ADLINK Technology China Co Ltd Address 300 Fang Chun Rd Zhangjiang Hi Tech Park Pudong New Area Shanghai 201203 Ch...

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