ADLINK Technology Q7-AL, User Manual

Page: 33 / 95

Q7-AL
Pinouts and Signal Descriptions
23
3.3.7. LVDS
Signal Pin Description I/O PU/PD Comment
LVDS_A0-
LVDS_A1-
LVDS_A2-
LVDS_A3- 99
101
103
105
107
109
113
115 LVDS Channel A differential pairs O
LVDS LVDS is default
(through eDP to
LVDS bridge)
Note: eDP support
is a build option
LV
LVDS_A_CK- 119
121 LVDS Channel A differential clock O
LVDS
LVDS_B0-
LVDS_B1-
LVDS_B2-
LVDS_B3- 100
102
104
106
108
110
114
116 LVDS Channel B differential pairs O
LVDS
LV
LVDS_B_CK- 120
122 LVDS Channel B differential clock O
LVDS
LVDS_3P3_VDD_EN 111 LVDS panel power enable O
3.3V
LVDS_3P3_BKLT_EN 112 LVDS panel backlight enable O
3.3V
LVDS_3P3_BKLT_CTRL 123 LVDS panel backlight brightness control O
3.3V
ePD to LVDS
requirement
3P3_LVDS_DDC_CLK 127 DDC lines used for flat panel detection
and control O
3.3V PU 2.2k 3.3V
3P3_LVDS_DDC_DAT 125 DDC lines used for flat panel detection
and control I/O
3.3V PU 2.2k 3.3V
3.3.8. eDP Build Option
Signal Pin Description I/O PU/PD Comment
e
eDP0_TX2-
e
eDP0_TX1-
e
eDP0_TX0- 107
109
103
105
99
101
eDP differential pairs O
PCIE AC coupled on
module
e
eDP0_TX3- 113
115 eDP differential pairs O
PCIE AC coupled on
module
e 119 eDP AUX+ I/O
PCIE AC coupled on
module
eDP0_AUX- 121 eDP AUX- I/O
PCIE AC coupled on
module
eDP0_HPD# 126 embedded DisplayPort Hotplug detection I
3.3V
eDP1_HPD# 128 embedded DisplayPort Hotplug
detection I
3.3V