ADLINK Technology PCI-8213, User Manual

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Bypass and WDT
5.2.3 Programming information of the WDT
Search Intel 21154 PCI-to-PCI bridge
The first step of programming the WDT is to use the 21554 chip
information (Vendor ID=1011h, Device ID=0026h, Class Code = 0604h)
to search the PCI-8214 card. If the card does exist, then record the
bridge’s location (Bus number, Device number and function number) for
the further programming.
GPIO Programming on 21154 Chip
The GPIO0~GPIO3 pins of the 21154 chip are used to control the WDT.
The following tables list the detailed bit mapping of 65h & 66h register.
GPIO Output Data Register – Offset 65h
Bit Name R/W
Description
3:0
GPIO output
Write-1-to-clear
R/W1TC
The gpio<3:0> pin output data write-1-
to-clear. Writing 1 to any of these bits
drives the corresponding bit low on the
gpio<3:0> bus if it is programmed as bi-
directional. Data is driven on the PCI
clock cycle following completion of the
configuration write to this register. Bit
positions corresponding to gpio pins that
are programmed as input only are not
driven. Writing 0 to thes e bits has no
effect. When read, reflects the last value
written.
7:4
GPIO output
Write-1-to-set
R/W1TS
The gpio<3:0> pin output data write-1-
to-set. Writing 1 to any of these bits
drives the corresponding bit high on the
gpio<3:0> bus if it is programmed as bi-
directional. Data is driven on the PCI
clock cycle following completion of the
configuration write to this register. Bit
positions corresponding to gpio pins that
are programmed as input only are not
driven Writing 0 to these bits has no
effect. When read, reflects the last value
written.
GPIO Output Enable Control Register – Offset 66h
Bit Name R/W Description
3:0
GPIO output
enable
Write-1-to-clear
R/W1TC
The gpio<3:0> pin output data write-1-
to-enable. Writing 1 to any of these bits
drives the corresponding gpio<3:0> pin
as input only; that is, the output driver is
tristated. Writing 0 to this register has no
effect. When read, reflects the last value
written.