Award BIOS Setup
43
DRAM Clock/Drive Control:
Phoenix - AwardBIOS CMOS Setup Utility
DRAM Clock/Drive Control
Current FSB Frequency
Current DRAM Frequency
DRAM Clock
DRAM Timing
DRAM CAS Latency
Bank Interleave
Precharge to Active (Trp)
Active to Precharge (Tras)
Active to CMD (Trcd)
DRAM Command Rate
133 MHz
133 MHz
By SPD
By SPD
2.5
Disabled
3T
6T
3T
2T Command
Item Help
____________________________
Menu Level
Ø
↑↓→←
Move Enter: Select +/-/PU/PD: Value F10: Save ESC: Exit F1: General Help
F5: Previous Values F6: Fail-safe defaults F7: Optimized Defaults
Current FSB / DRAM Frequency:
Option N/A
This item can display the current FSB / DRAM Frequency.
DRAM Clock:
This selecting option allows you to control the DRAM speed.
The choice: 100 MHz, 133 MHz and By SPD.
DRAM Timing:
The function allows you to enable or disable the DRAM timing by SPD.
The choice: Manual, By SPD.
DRAM CAS Latency:
When synchronous DRAM is installed, the number of clock cycles of CAS
latency depends on the DRAM timing.
The choice: 2, and 2.5.
Bank Interleave:
The item allows you to set how many banks of SDRAM support in your SBC
card.
The choice: Disabled, 2 Bank and 4 Bank
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