Chapter 3
Hardware
24
Reference Manual
CoreModule 740
26
IDE_PDD2
Primary Disk Data 2
27
FDD_DS0
Floppy Drive Select 0 – Selects drive 0
28
IDE_PDD13
Primary Disk Data 13
29
GND15
Floppy Ground
30
IDE_PDD1
Primary Disk Data 1
31
NC
Not Connected
32
IDE_PDD14
Primary Disk Data 14
33
GND16
Floppy Ground
34
IDE_PDD0
Primary Disk Data 0
35
FDD_DIR*
Floppy Direction – Direction of head movement (0 = inward motion, 1 =
outward motion)
36
IDE_PDD15
Primary Disk Data 15
37
GND17
Floppy Ground
38
GND1
IDE Ground
39
FDD_STEP*
Floppy Step – Low pulse for each track-to-track movement of the head
40
HD_KEY
Not Connected
41
GND18
Floppy Ground
42
IDE_PDDREQ
Primary DMA Channel Request – Used for DMA transfers between host
and drive (direction of transfer controlled by PIOR* and PIOW*). Used in
asynchronous mode with PDACK*. Drive asserts PDREQ when ready to
transfer or receive data.
43
FDD_WDATA
Floppy Write Data – Encoded data to the drive for write operations
44
GND2
IDE Ground
45
GND19
Floppy Ground
46
IDE_PDIOW*
Primary I/O Write Strobe – Strobe signal for write functions. Negative
edge enables data from a register or data port of the drive onto the host
data bus. Positive edge latches data at the host.
47
FDD_WGATE*
Floppy Write Gate – Signal to the drive to enable current flow in the write
head
48
GND7
IDE Ground
49
GND20
Floppy Ground
50
IDE_PDIOR*
Primary I/O Read Strobe – Strobe signal for read functions. Negative edge
enables data from a register or data port of the drive onto the host data bus.
Positive edge latches data at the host.
51
FDD_TRK0*
Floppy Track 0 – Senses the head is positioned over track 0
52
GND6
IDE Ground
53
GND21
Floppy Ground
54
IDE_PDIORDY
Primary I/O DMA Channel Ready – When negated extends the host
transfer cycle of any host register access when the drive is not ready to
respond to a data transfer request. High impedance if asserted.
55
FDD_WPRT*
Floppy Write Protect – Senses the diskette is write protected
Table 3-5. Utility 2 Interface Pin Signals (J4) (Continued)