ADLINK Technology COM Express cExpress-TL User Manual Download

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cExpress-TL User’s Guide

PICMG COM.0 R3.0

Page 25

4.3.

AB Connector Signal Descriptions

4.3.1

Audio

Name

Pin #

Description

I/O

PU / PD Comment

AC_RST# /
HDA_RST#

A30

Reset output to CODEC, active low.

O
3.3VSB

AC_SYNC /
HDA_SYNC

A29 Sample-synchronization

signal to the CODEC(s).

O
3.3VSB

AC_BITCLK /
HDA_BITCLK

A32

Serial data clock generated by the external CODEC(s). I/O

3.3VSB

AC_SDOUT /
HDA_SDOUT

A33

Serial TDM data output to the CODEC.

O
3.3VSB

AC_SDIN[2:0] /
HDA_SDIN[2:0]

B28- B30 Serial TDM data inputs from up to 3 CODECs.

I/O
3.3VSB

B28 Not supported
Tiger Lake UP3 doesn’t offer this pin

Summary of Contents for COM Express cExpress-TL

Page 3: ...ctrical and Electronic Equipment WEEE directive Environmental protection is a top priority for ADLINK We have enforced measures to ensure that our products manufacturing processes components and raw m...

Page 4: ...s cables when installing mounting or un installing removing equipment To avoid electrical shock and or damage to equipment Keep equipment away from water or liquid sources Keep equipment away from hig...

Page 5: ...enoting special levels of information Note This information adds clarity or specifics to text and illustrations Caution This information indicates the possibility of minor physical injury component da...

Page 6: ...Jose CA 95138 USA Tel 1 408 360 0200 Toll Free 1 800 966 5200 USA only Fax 1 408 360 0222 Email info adlinktech com ADLINK Technology China Co Ltd 300 Fang Chun Rd Zhangjiang Hi Tech Park Pudong New...

Page 7: ...2 6 Multi I O and Storage 14 2 7 Trusted Platform Module TPM 15 2 8 SEMA Board controller 15 2 9 Debug 15 2 10 Power 16 2 11 Mechanical and Environmental 16 3 Block Diagram 18 4 Pinout and Signal Des...

Page 8: ...6 PCIe Graphics Port PEG 53 4 4 7 Module Type Definition 54 4 4 8 Power and Ground 55 5 Additional Features 56 5 1 Debug Connector 57 5 2 Status LEDs 58 5 3 Exception Codes 59 5 4 Fan Connector 60 5 5...

Page 9: ...function diagram 18 Figure 2 Module rear side row and pin numbering 19 Figure 3 Module feature locations 56 Figure 4 cExpress TL and Debug Module 57 Figure 5 Module mechanical dimensions 65 Figure 6 H...

Page 10: ...y capacity wide operating temperature range and MIL STD environmental specifications make it well suited for mission critical or extreme rugged applications The integrated Intel Iris Xe Graphics Gen12...

Page 11: ...Core i5 1145GRE 2 6 4 1 GHz 8MB 28W 15W 12W cTDP 4C Iris Xe IBECC non ECC Intel Core i3 1115GRE 3 0 3 9 GHz 6MB 28W 15W 12W cTDP 2C UHD IBECC non ECC Supporting Intel VT Intel VT d Intel TXT Intel SSE...

Page 12: ...DS graphics outputs 4x 4K 60Hz eDP optional in place of LVDS VGA optional in place of DDI 3 Encode transcode HD content Playback of high definition content including Blu ray Disc and Blu ray Disc 3D c...

Page 13: ...Hz bpp with DSC DDI x3 Digital Display Ports DDI support DisplayPort 1 4a HDMI 2 0b or DVI VGA VGA BOM option support in place of DDI 3 max resolution 1920x1200 60Hz 2 3 Audio Intel HD Audio integrate...

Page 14: ...1 USB 0 1 2 3 4x USB 2 0 1 1 USB 4 5 6 7 SuperSpeedPlus SuperSpeed High Speed Full Speed and Low Speed USB signalling Note Carrier board must be designed for Gen2 operation UART Two UART interfaces S...

Page 15: ...is BOM option 2 8 SEMA Board controller Supports Voltage current monitoring power sequence debug support AT ATX mode control logistics and forensic information flat panel control general purpose I2C f...

Page 16: ...on USB S3 S4 WoL S3 S4 S5 ECO Mode support for deep S5 for 5Vsb power saving Power Consumption Please contact your ADLINK representative for the document COM Express Module Power Consumption 2 11 Mech...

Page 17: ...yright 2021 ADLINK Technology Inc Shock and Vibration IEC 60068 2 64 and IEC 60068 2 27 MIL STD 202F Method 213B Table 213 I Condition A and Method 214A Table 214 I Condition D HALT tested Thermal Str...

Page 18: ...VGA eDP LVDS USB 2 0 Lane 0 7 SATA Port 0 1 SATA Port 2 3 Max 2 5GbE PCIe Lane 0 3 PCIe Lane 4 PCIe Lane 5 HDA SPI SMBus I2C GPIO SDIO UART CAN LPC eSPI 4 PCIe Gen3 HSIO 4 7 eSPI TPM 2 0 build option...

Page 19: ...e below is a comprehensible list of all signal pins supported on the dual 220 pin COM Express connectors as defined for Type 6 in the PICMG COM 0 R3 0 specification Signals described in the specificat...

Page 20: ...R6 D15 DDI1_CTRLCLK_AUX A16 SATA0_TX B16 SATA1_TX C16 DDI1_PAIR6 D16 DDI1_CTRLDATA_AUX A17 SATA0_TX B17 SATA1_TX C17 RSVD D17 RSVD A18 SUS_S4 B18 SUS_STAT ESPI_RESET C18 RSVD D18 RSVD A19 SATA0_RX B19...

Page 21: ...LPC_SERIRQ ESPI_CS1 B50 CB_RESET C50 DDI3_PAIR3 D50 DDI2_PAIR3 A51 GND FIXED B51 GND FIXED C51 GND FIXED D51 GND FIXED A52 PCIE_TX5 B52 PCIE_RX5 C52 PEG_RX0 D52 PEG_TX0 A53 PCIE_TX5 B53 PCIE_RX5 C53 P...

Page 22: ...84 GND D84 GND A85 GPI3 B85 VCC_5V_SBY C85 PEG_RX10 D85 PEG_TX10 A86 RSVD B86 VCC_5V_SBY C86 PEG_RX10 D86 PEG_TX10 A87 eDP_HPD B87 VCC_5V_SBY C87 GND D87 GND A88 PCIE0_CK_REF B88 BIOS_DIS1 C88 PEG_RX1...

Page 23: ...09 VCC_12V D109 VCC_12V A110 GND FIXED B110 GND FIXED C110 GND FIXED D110 GND FIXED Note STRIKETHROUGH strike through entries are not supported functions on this product PCIe lane 5 6 7 are BOM option...

Page 24: ...3V tolerant I O 5V Bi directional signal 5V tolerant I O 3 3VSB Input or output 3 3V tolerant active in standby state DDC Display Data Channel PCIE PCI Express compatible differential signal PEG PCI...

Page 25: ...t to CODEC active low O 3 3VSB AC_SYNC HDA_SYNC A29 Sample synchronization signal to the CODEC s O 3 3VSB AC_BITCLK HDA_BITCLK A32 Serial data clock generated by the external CODEC s I O 3 3VSB AC_SDO...

Page 26: ...o drive a 37 5 Ohm equivalent load O Analog PD 150R VGA_BLU B92 Blue for monitor Analog DAC output designed to drive a 37 5 Ohm equivalent load O Analog PD 150R VGA_HSYNC B93 Horizontal sync output to...

Page 27: ...elow Pin LVDS mode eDP mode A71 A72 LVDS_A0 LVDS_A0 eDP_TX2 eDP_TX2 A73 A74 LVDS_A1 LVDS_A1 eDP_TX1 eDP_TX1 A75 A76 LVDS_A2 LVDS_A2 eDP_TX0 eDP_TX0 A78 A79 LVDS_A3 LVDS_A3 A81 A82 LVDS_A_CK LVDS_A_CK...

Page 28: ...LVDS_B0 LVDS_B0 LVDS_B1 LVDS_B1 LVDS_B2 LVDS_B2 LVDS_B3 LVDS_B3 B71 B72 B73 B74 B75 B76 B77 B78 LVDS Channel B differential pairs O LVDS LVDS_B_CK LVDS_B_CK B81 B82 LVDS Channel B differential clock...

Page 29: ...ifferential pairs O PCIE AC coupled off module eDP_VDD_EN A77 eDP power enable O 3 3V PD 100K eDP_BKLT_EN B79 eDP backlight enable O 3 3V PD 100K eDP_BKLT_CTRL B83 eDP backlight brightness control O 3...

Page 30: ...sec link indicator active low OD 3 3VSB GBE0_LINK1000 A5 Gigabit Ethernet Controller 0 1000Mbit sec link indicator active low OD 3 3VSB GBE0_CTREF A14 Reference voltage for Carrier Board Ethernet chan...

Page 31: ...ve Input differential pair I SATA AC coupled on Module SATA2_TX SATA2_TX A22 A23 Serial ATA channel 2 Transmit Output differential pair O SATA Not supported SATA2_RX SATA2_RX A25 A26 Serial ATA channe...

Page 32: ...ferential pair I PCIE AC coupled off Module PCIE_TX3 PCIE_TX3 A58 A59 PCI Express channel 3 Transmit Output differential pair O PCIE AC coupled on Module PCIE_RX3 PCIE_RX3 B58 B59 PCI Express channel...

Page 33: ...ssignments Name HSIO name on SOC Comment PCIE0 HSIO 4 PCIE1 HSIO 5 PCIE2 HSIO 6 PCIE3 HSIO 7 PCIE4 HSIO 9 PCIE5 N A BOM option support by project basis through a PCIe switch PCIE6 N A BOM option suppo...

Page 34: ...exed address command and data bus I O 3 3VSB LPC_FRAME B3 LPC frame indicates the start of an LPC cycle O 3 3VSB LPC_DRQ0 LPC_DRQ1 B8 B9 LPC serial DMA request I 3 3V Not connected LPC_SERIRQ A50 LPC...

Page 35: ...ta pairs for Port 5 I O 3 3VSB USB 1 1 2 0 compliant USB7 USB7 B37 B37 USB differential data pairs for Port 6 I O 3 3VSB USB 1 1 2 0 compliant USB_0_1_OC B44 USB over current sense USB ports 0 and 1 s...

Page 36: ...A94 Clock from module to carrier board SPI BIOS flash O 3 3VSB SPI_POWER A91 Power supply for Carrier Board SPI sourced from Module nominally 3 3V The Module shall provide a minimum of 100mA on SPI_PO...

Page 37: ...TRIP A35 Active low output indicating that the CPU has entered thermal shutdown O 3 3VSB PU 10K 3 3VSB FAN_PWMOUT B101 Fan speed control Uses the Pulse Width Modulation PWM technique to control the fa...

Page 38: ...d main power rails I O OD 3 3VSB PU 2 2K 3 3VSB SMB_ALERT B15 System Management Bus Alert active low input can be used to generate an SMI System Management Interrupt or to wake the system Power source...

Page 39: ...GPI 1 A63 General purpose input pins Pulled high internally on the module I 3 3V PU 10K 3 3V GPI 2 A67 General purpose input pins Pulled high internally on the module I 3 3V PU 10K 3 3V GPI 3 A85 Gene...

Page 40: ...operation used to notify LPC devices O 3 3VSB SUS_S3 A15 Indicates system is in Suspend to RAM state Active low output An inverted copy of SUS_S3 on the carrier board also known as PS_ON may be used t...

Page 41: ...used P 8 5 20 V VCC_5V_SBY B84 B85 B86 B87 Standby power input 5 0V nominal If VCC5_SBY is used all available VCC_5V_SBY pins on the connector s shall be used Only used for standby and suspend functi...

Page 42: ...module USB_SSTX1 USB_SSTX1 D6 D7 Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB1 O PCIE AC coupled on module USB_SSRX2 USB_SSRX2 C9 C10 Additional Receive signal...

Page 43: ...I Express channel 7 Transmit Output differential pair O PCIE AC coupled on Module By a PCIe switch project basis PCIE_RX7 PCIE_RX7 C22 C23 PCI Express channel 7 Receive Input differential pair I PCIE...

Page 44: ...PAIR5 DDI1_PAIR5 C29 C30 DDI1_PAIR6 DDI1_PAIR6 C15 C16 DDI1_HPD C24 DP1_HPD HDMI1_HPD DDI1_CTRLCLK_AUX D15 DP1_AUX HMDI1_CTRLCLK DDI1_CTRLCLK_AUX D16 DP1_AUX HMDI1_CTRLDATA DDI1_DDC_AUX_SEL D34 DDI1_D...

Page 45: ...nplug and notification of the link layer I 3 3V PD 100K Module must tolerate high level in stand by mode The carrier board shall include a blocking FET on DP1_HPD to prevent back drive current from da...

Page 46: ...rs shall be placed on the Carrier TMDS1_CLK TMDS1_CLK D36 D37 HDMI Port Differential Pair Clock Lines HDMI_HPD C24 Detection of Hot Plug Unplug and notification of the link layer I 3 3V PD 100K HDMI1_...

Page 47: ...TMDS2_CLK DDI2_HPD D44 DP2_HPD HDMI2_HPD DDI2_CTRLCLK_AUX C32 DP2_AUX HMDI2_CTRLCLK DDI2_CTRLCLK_AUX C33 DP2_AUX HMDI2_CTRLDATA DDI2_DDC_AUX_SEL C34 DDI2_DDC_AUX_SEL DDI2_DDC_AUX_SEL Note Dual Mode HD...

Page 48: ...nplug and notification of the link layer I 3 3V PD 100K Module must tolerate high level in stand by mode The carrier board shall include a blocking FET on DP1_HPD to prevent back drive current from da...

Page 49: ...rs shall be placed on the Carrier TMDS2_CLK TMDS2_CLK D49 D50 HDMI Port Differential Pair Clock Lines HDM2_HPD D44 Detection of Hot Plug Unplug and notification of the link layer I 3 3V PD 100K HDMI2_...

Page 50: ...TMDS3_CLK DDI3_HPD C44 DP3_HPD HDMI3_HPD DDI3_CTRLCLK_AUX C36 DP3_AUX HMDI3_CTRLCLK DDI3_CTRLCLK_AUX C37 DP3_AUX HMDI3_CTRLDATA DDI3_DDC_AUX_SEL C38 DDI3_DDC_AUX_SEL DDI3_DDC_AUX_SEL Note Dual Mode HD...

Page 51: ...nplug and notification of the link layer I 3 3V PD 100K Module must tolerate high level in stand by mode The carrier board shall include a blocking FET on DP1_HPD to prevent back drive current from da...

Page 52: ...rs shall be placed on the Carrier TMDS3_CLK TMDS3_CLK C49 C50 HDMI Port Differential Pair Clock Lines HDM3_HPD C44 Detection of Hot Plug Unplug and notification of the link layer I 3 3V PD 100K HDMI3_...

Page 53: ...E_TX 16 31 and in Module pin out Type 6 I PCIE AC coupled off Module PEG_TX2 PEG_TX2 D58 D59 PCI Express Graphics transmit differential pairs These are the same lines as PCIE_TX 16 31 and in Module pi...

Page 54: ...present X TYPE2 TYPE1 TYPE0 X X X Pinout Type 1 X X X Pinout Type 10 NC NC NC Pinout Type 2 NC NC GND Pinout Type 3 NC GND NC Pinout Type 4 NC GND GND Pinout Type 5 GND NC NC Pinout Type 6 GND NC GND...

Page 55: ...D105 D106 D107 D108 D109 Primary power input supports wide range 5 20V input All available VCC_12V pins on the connector s shall be used P 8 5 20 V GND C1 C2 C5 C8 C11 C14 C21 C31 C41 C51 C60 C70 C73...

Page 56: ...chapter describes connectors LEDs switches and additional items located on the module and not necessarily included in the PICMG standard spec ification The locations of these items is as below Figure...

Page 57: ...particular useful during carrier design and bring up phase It offers access to the following critical parts of the module z Test points measurement of internal power rails z I2C bus for BIOS POST cod...

Page 58: ...n Codes below LED2 Green Power Source 3Vcc S0 LED ON S3 S4 S5 LED OFF ECO mode LED OFF LED3 Red BMC output and same signal as WDT B27 on BtB connector Module power up WD LED LED OFF Watchdog counting...

Page 59: ...xception Codes Exception Code Error Message 0 NOERROR 3 NO_SLP_S5 4 NO_SLP_S4 5 NO_SLP_S3 6 BIOS_FAIL 7 RESET_FAIL 8 RESETIN_FAIL 9 NO_CB_PWROK 10 CRITICAL_TEMP 11 POWER_FAIL 12 VOLTAGE_FAIL 13 RSMRST...

Page 60: ...Express TL User s Guide PICMG COM 0 R3 0 Page 60 Copyright 2021 ADLINK Technology Inc 5 4 Fan Connector Connector type JVE 24W1125A 04M00 Name Description 1 FAN_PWMOUT 2 FAN_TACHIN 3 GND 4 12V 4 3 2 1...

Page 61: ...t of BIOS default settings perform the following steps 1 Shut down the system 2 Keep the BIOS Setup Defaults Reset Button pressed and boot up the system You can release the button when the BIOS prompt...

Page 62: ...in the SPI0 slot on the carrier In dual BIOS Failsafe mode both BIOS chips on the module are configured as SPI1 Only one of the two is connected to the SPI bus at any given time In case of failure of...

Page 63: ...he task the system is currently executing Checkpoints are very useful in aiding software developers or technicians in debugging problems that occur during the pre boot process on production hardware A...

Page 64: ...Page 64 Copyright 2021 ADLINK Technology Inc 7 Software Support 7 1 Windows 10 IOT Enterprise 64 bit 7 2 Yocto Linux 64 bit https github com ADLINK meta adlink x86 64bit TBC 7 3 Ubuntu Under planning...

Page 65: ...chanical dimensions 0 0 4 16 5 74 2 80 95 4 91 4 8 9 91 4 32 7 91 6 18 95 74 514 52 5 connector on bottom side 5 3 4 2 Top View Side View All dimensions are shown in millimeters Tolerances should be 0...

Page 66: ...ss TL User s Guide PICMG COM 0 R3 0 Page 66 Copyright 2021 ADLINK Technology Inc 95 95 76 65 87 11 5 M2 5 4pcs M2 5 2pcs 8 2 Thermal Solutions 8 2 1 Heatspreader HTS Figure 6 Heatspreader HTS Dimensio...

Page 68: ...ress TL User s Guide PICMG COM 0 R3 0 Page 68 Copyright 2021 ADLINK Technology Inc 25 1 95 95 76 87 5 M2 5 4pcs M2 5 2pcs 8 2 3 Heatsink High Profile THSH Figure 8 Heatsink High Profile THSH Dimension...

Page 69: ...Express TL User s Guide PICMG COM 0 R3 0 Page 69 Copyright 2021 ADLINK Technology Inc 39 4 5 95 95 76 87 M2 5 x4pcs M2 5 2pcs 8 2 4 Heatsink with Fan THSF Figure 9 Heatsink with Fan THSF Dimensions mm...

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