cExpress-TL User’s Guide
PICMG COM.0 R3.0
Page 45
Copyright © 2021 ADLINK Technology, Inc.
4.4.3.1.
Displayport (DP) Mode
Name
Pin #
Description
I/O
PU / PD
Comment
DP
DP1_LANE0-
DP
DP1_LANE1-
DP
DP1_LANE2-
DP
DP1_LANE3-
D26
D27
D29
D30
D32
D33
D36
D37
DP Port 1, differential pair data lines
O PCIE
AC coupled off Module
100 nF DC blocking capacitors
shall
be placed on
the Carrier
DP1_HPD C24
DP Port 1, detection of Hot Plug / Unplug and
notification of the link layer
I 3.3V
PD 100K
Module must tolerate high level in stand-by mode.
The carrier board shall include a blocking FET on
DP1_HPD to prevent back-drive current from
damaging the Module.
D15
DP Port 1, Bidirectional Channel used for Link
Management and Device Control
I/O PCIE
PD 100K
AC coupled on Module
DP1_AUX- D16
DP Port 1, Bidirectional Channel used for Link
Management and Device Control
I/O PCIE
PU 100K
AC coupled on Module
DDI1_DDC_AUX_SEL D34
Strapping Signal to select HDMI or DP output
1M pull-down to logic ground enables HDMI
Floating enables Displayport mode
I 3.3V
PD 1M
DP mode enabled
