cExpress-TL User’s Guide
PICMG COM.0 R3.0
Page 18
Copyright © 2021 ADLINK Technology, Inc.
3.
Block Diagram
C
AB
DDI 1
DDI 2
DDI 3
USB 3.0 Lane 3
USB 3.0 Lane 2
USB 3.0 Lane 1
USB 3.0 Lane 0
PCIe Lane 6-7
PEG Port
PCIe 16 -19
PCIe 20 - 31
11th Generation
Intel® Core™, Celeron
®
ULT
(formerly Tiger Lake-UP3
)
DP to VGA
eDP to LVDS
(build option)
(build option), eDP 4lanes
SATA 6Gb/s
DDR4 SODIMM
(top side)
3200 MT/s, non-ECC/IBECC
LAN
Controller
VGA
eDP/LVDS
USB 2.0 Lane 0-7
SATA Port 0-1
SATA Port 2-3
Max. 2.5GbE
PCIe Lane 0-3
PCIe Lane 4
PCIe Lane 5
HDA
SPI
SMBus
I2C
GPIO/SDIO
UART/CAN
LPC/eSPI
4 PCIe Gen3
(HSIO 4-7)
eSPI
TPM 2.0
(build option)
eSPI to LPC
I2C
HSUART
Thermal
Sensor
(board)
1 PCIe Gen4 x4
DDI B
(DP, HDMI)
Embedded Controller
1 x4, 2 x2, 4 x1
1 PCIe Gen3
(HSIO 9)
DDI A
TCP0
TCP1
DDI B
USB 3.2 Gen2 x1
USB 3.2 Gen2 x1
USB 3.2 Gen2 x1
USB 3.2 Gen2 x1
PCIe Gen3/2
Switch
2 x1 only
1 PCIe Gen3
(HSIO 8)
TSN dependent on controller SKU
BIOS
BIOS
DB30 x86
connector
(build option)
DDR4 SODIMM
(bottom side)
3200 MT/s, non-ECC/IBECC
SMBus
Figure 1 – Module function diagram
