Actel Core1553, User Manual, Page: 9 / 38

9
1 – Core1553 Development Kit Hardware
Core1553BRM IP Core
Actel Core1553BRM provides a complete MIL-STD-1553B bus controller (BC), remote terminal (RT),
or bus monitor terminal (BM or MT). Core1553BRM can be configured to provide all three 1553
functions or any combination thereof. The core is supported in all recent Actel flash, antifuse, and
radiation-tolerant product families. A typical system implementation using Core1553BRM is shown
in
Figure 1-1 .
A typical Core1553BRM system requires a connection to an external CPU, used to set up the core
registers and initialize the data tables in memory. To facilitate system integration, Core153BRM is
register-compatible with the SUMMIT
TM
family of 1553B devices from Aeroflex
®
.
The external memory block is used to store the received and transmitted data. This memory can be
internal or external to the FPGA, depending upon the family targeted. The core interfaces to the
1553 bus through an external 1553 transceiver and transformer.
Core1553BRM is available in the following versions:
• An evaluation version that allows core simulation with Actel Libero IDE or ModelSim
®
.
• An obfuscated version that provides obfuscated RTL and precompiled testbenches.
• An RTL version with full access to the source code.
Refer to the Core1553BRM Handbook for more information.
Figure 1-1 • Typical Core1553 Application
Actel FPGA
Memory
Core1553BRM
Master
CPU
Glue
Logic
Backend
Interface
CPU
Interface
1553B
Encoders
and
Decoders
Protocol
Controller
Pulse
Transformer
Pulse
Transformer
Transceiver
Not Included