Actel Core1553, User Manual, Page: 13 / 38

13
2 – Core1553BRM Demonstration Design
The Core1553BRM demonstration design implements two complete Core1553BRM cores into a
single M1AFS1500 FPGA and allows you to evaluate the 1553 bus controller, remote terminal, and
bus monitor (monitor terminal) functions of the core (
Figure 2-1 ). In addition, the design allows for
the monitoring of 1553B bus activity using Actel Silicon Explorer II hardware.
FPGA Design
The demonstration design contained within the M1AFS1500 FPGA consists of the following blocks:
• Two complete Core1553BRM cores
• 1553B bus interface
• Memory interface
• Bus arbiter
• Control sequencer
• UART
• DIP switches
• LEDs
• Data generator
• External memory
Figure 2-1 • Core1553BRM Demo Design Architecture
C ontroller
S e q uen c er
C ore1553BRM
UNIT1
1553B
Interfa c e
Bus Ar b iter
1553B
Trans c eiver
Memory
2 Pa g es Ea c h
6 4 K×1 6
UART
Terminal
Memory
Interfa c e
Data
G enerator
DIP
S wit c h
LEDs
1553 Bus
M1AF S 1500
C ore1553BRM
UNIT2