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Actel Core1553 User Manual Download Page 37

50200184-0/8.09

Actel Corporation

2061 Stierlin Court
Mountain View, CA
94043-4655 USA

Phone 

650.318.4200

Fax

 650.318.4600

Actel Europe Ltd.

River Court,Meadows Business Park
Station Approach, Blackwater
Camberley Surrey GU17 9AB
United Kingdom

Phone 

+44 (0) 1276 609 300

Fax 

+44 (0) 1276 607 540

Actel Japan

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Tokyo 150  Japan

Phone 

+81.03.3445.7671

Fax 

+81.03.3445.7668

http://jp.actel.com

Actel Hong Kong

Room 2107, China Resources Building
26 Harbour Road
Wanchai, Hong Kong

Phone 

+852 2185 6460

Fax 

+852 2185 6488

www.actel.com.cn

Actel, IGLOO, Actel Fusion, ProASIC, Libero, Pigeon Point and the associated logos are trademarks or registered 

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Actel is the leader in low-power and mixed-signal FPGAs and offers the most comprehensive portfolio of 
system and power management solutions. Power Matters. Learn more at www.actel.com.

Summary of Contents for Core1553

Page 1: ...Core1553 Development Kit User s Guide...

Page 2: ...ss for a particular purpose Information in this document is subject to change without notice Actel assumes no responsibility for any errors that may appear in this document This document contains conf...

Page 3: ...Display 17 Script Mode Demonstration Design 19 Auto Mode Demonstration Design 22 Monitoring 1553B Message Traffic Using Silicon Explorer II 24 Interrupt Status Messages 25 Subaddresses 26 3 Modifying...

Page 4: ......

Page 5: ...Kit board and 1553 bus physical connections are included on the Core1553 Daughter Card which plugs directly onto the Fusion Advanced Development Kit board Once programmed the development board provide...

Page 6: ...t file for testing the demo in script mode Designer_adb ADB file for the demonstration design RTL FPGA example design source files Note Core1553BRM source files are not provided in the CORE1553 Develo...

Page 7: ...ion HyperTerminal or similar serial communication program PC system running Windows XP operating system or later FlashPro software v8 5 or later Optional Items Core1553BRM obfuscated or RTL license Li...

Page 8: ......

Page 9: ...h the SUMMITTM family of 1553B devices from Aeroflex The external memory block is used to store the received and transmitted data This memory can be internal or external to the FPGA depending upon the...

Page 10: ...allel flash and SPI flash I2 C interface organic light emitting diode OLED Temperature diode potentiometer and pulse width modulation PWM circuit Mixed signal header for several daughter boards to be...

Page 11: ...rmer Coupling Figure 1 4 on page 1 12 Both Bus A and Bus B Figure 1 3 Core1553 Daughter Card Table 1 Core1553 Daughter Card Components Component Part Number Manufacturer Location 1553B transceiver BU...

Page 12: ...scribed in Table 1 1 Figure 1 4 Jumpers J5 and J7 Settings Table 1 1 Jumper JP11 and JP17 Settings Jumper Function Default Setting JP11 Jumper to select either external 3 3 V or 3 3 V provided through...

Page 13: ...g Actel Silicon Explorer II hardware FPGA Design The demonstration design contained within the M1AFS1500 FPGA consists of the following blocks Two complete Core1553BRM cores 1553B bus interface Memory...

Page 14: ...memory space Bus Arbiter This block allows the control sequencer block and the two Core1553BRM cores to access the internal bus Control Sequencer The control sequencer connects to the BRM CPU interfa...

Page 15: ...h UART 2 Sets frame time to 0 75 seconds 3 RT to BC transfer SA 25 WC 9 RT to transmit the data from Data generator block 4 BC generates an interrupt 5 BC to RT transfer SA 2 WC 9 BC will transmit its...

Page 16: ...M core will use in Qualification mode Switch 3 is the parity and 4 to 8 are the RT address LEDs There are twelve LEDs Figure 2 3 on the board used to indicate the status of the two BRM cores and the m...

Page 17: ...give information regarding the core configuration This information is displayed in the following form Core1553BRM XYZZ The meaning of these codes depends upon the mode in which the core was powered u...

Page 18: ...RM unit 1 to 1234h BRM1 R1 00 0000 1234 RETURN Display memory at location 0a00 BRM1 M 0a00 RETURN Set memory at location 0a00 of BRM unit 1 to value 1234h BRM1 M1 0a00 0000 1234 RETURN Note The system...

Page 19: ...g the supply into an electrical outlet 3 Set the DIP switch at S1 to the default configuration of 00011010 Note These switches are wired to inputs of the FPGA so that open will correspond to logic 1 4...

Page 20: ...indicates that bus loopback is enabled 00 indicates the remote terminal address is set to 00 Note If the display shows any other message check the DIP switch settings 3 Press ESC to enter command mod...

Page 21: ...pleted correctly Figure 2 7 The HyperTerminal session will echo the commands sent to configure various register and memory settings At the end of the download the session will return to the prompt as...

Page 22: ...by the control sequencer These 1553B messages can be monitored using an external bus monitor on Silicon Explorer Setting Up the Demonstration Design The Core1553BRM Development Kit boards come preprog...

Page 23: ...ort in parentheses identifies the COM port assigned to this device Figure 2 10 If you do not see CP2102 you need to install the CP210x_Drivers driver Refer to Installing the M1AFS ADV DEV KIT Board US...

Page 24: ...alyzer The next section will describes monitoring 1553B message using Silicon Explorer II but you can follow the similar steps when using the logic analyzer To monitor message traffic 1 If you do not...

Page 25: ...from the Silicon Explorer software You should see Bus Activity on Bus A Figure 2 13 Interrupt Status Messages Core1553BRM will generate status messages of the format N IAW IIW MIW on HyperTerminal N I...

Page 26: ...rds bus A This pattern repeats with the word count increasing on the third message Refer to the Interrupts section of the Core1553BRM Handbook for more information Subaddresses Subaddressing enables d...

Page 27: ...m Refer to the Core1553BRM Handbook for more information Scripting High level command files created to control the core operation can be converted into log files by the verification testbench These lo...

Page 28: ......

Page 29: ...Launch the Actel FlashPro programming software When using the FlashPro programming software the programmer selects FlashPro3 The programming stick is functionally equivalent to a FlashPro programmer...

Page 30: ......

Page 31: ...UART interface schematic on the M1AFS ADV DEV KIT board With a USB driver properly installed and the correct COM port and communication settings selected you can use the HyperTerminal program to comm...

Page 32: ......

Page 33: ...omer Technical Support Center spends a great deal of time creating application notes and answers to FAQs So before you contact us please visit our online resources It is very likely we have already an...

Page 34: ...information to a queue where the first available application engineer receives the data and returns your call The phone hours are from 7 00 a m to 6 00 p m Pacific Time Monday through Friday The Techn...

Page 35: ...design 13 CORE1553 SA 5 Core15553 Development Kit Core1553 Daughter Card 11 Fusion Advanced Development Kit 10 customer service 33 D demonstration design Auto mode 22 Script mode 19 M M1AFS1500 5 M1A...

Page 36: ...x 81 03 3445 7668 http jp actel com Actel Hong Kong Room 2107 China Resources Building 26 Harbour Road Wanchai Hong Kong Phone 852 2185 6460 Fax 852 2185 6488 www actel com cn Actel is the leader in l...

Page 37: ...1 Fax 81 03 3445 7668 http jp actel com Actel Hong Kong Room 2107 China Resources Building 26 Harbour Road Wanchai Hong Kong Phone 852 2185 6460 Fax 852 2185 6488 www actel com cn Actel IGLOO Actel Fu...

Page 38: ...275 ISO 9001 7 812 627 14 35 sales st electron ru 198099 19 100 331...

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