Actel Core1553, User Manual, Page: 17 / 38

Interpreting the HyperTerminal Display
17
Data Generator
The gata generator block generates data for 1553B messages within the demonstration design.
This data are mainly used during Auto mode.
External Memory
Core1553BRM requires a connection memory interface. It supports up to 128 Kbytes of memory,
but it mainly depends on the design. In the demonstration design, the bus arbiter allows the
controller and two cores to access the memory, which provides 64 K words of memory for each of
the cores. The two on-board SRAMs on the M1-embedded Fusion Advanced Development Kit
board are used for that purpose.
Interpreting the HyperTerminal Display
Once programmed with the Core1553BRM demonstration design and the board is powered up, the
HyperTerminal display will give information regarding the core configuration. This information is
displayed in the following form:
Core1553BRM XYZZ
The meaning of these codes depends upon the mode in which the core was powered up.
Auto mode
While in Auto mode:
• X indicates which BRM core is configured as the bus controller.
• Y: L = Loopback mode; T = Transceiver mode.
• ZZ indicates the remote terminal address for the RT.
Example display:
Core1553BRM 1L02
Script mode (Non-Initialization mode)
While in Non-Initialization mode:
• X: N indicates Non-Initialization mode.
• Y: L = Loopback mode; T = Transceiver mode.
Table 2-1 • Demonstration Board LEDs
LED Board Location Function
1 D1 Heartbeat, flashes at 2 KHz
2 D2 Not used
3 D3 BRM core 1 busy
4 D4 BRM core 2 busy
5 D5 Data compare error
6 D6 Message of failure interrupt
7 D7 SRAM1 byte High enable
8 D8 SRAM1 byte Low enable
9 D9 SRAM2 byte High enable
10 D10 SRAM2 byte Low enable
11 D11 SRAM1 and SRAM2 output enable
12 D12 SRAM1 and SRAM2 write enable