Actel Core1553, User Manual, Page: 22 / 38

Core1553BRM Demonstration Design
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memory or register compare instructions failed ( Figure 2-8 ). LED D5 will light to indicate a memory
or register compare failure. Use RSTN and ESC to re-enter the command if an error is made.
Auto Mode Demonstration Design
The DIP switch setting enables you to set the core in Auto mode. In this mode and after power-up,
the control sequencer will automatically configure one Core1553BRM as a bus controller and the
other as a remote/monitor terminal (RT/MT). The BC is programmed to transmit data to and from
the RT as specified by the control sequencer. These 1553B messages can be monitored using an
external bus monitor on Silicon Explorer.
Setting Up the Demonstration Design
The Core1553BRM Development Kit boards come preprogrammed with demonstration designs. If
you want to reprogram the FPGA or if the FPGA is reprogrammed with a different design, follow
the steps in
"Programming the Fusion FPGA on M1AFS-ADV-DEV-KIT" section on page A-29 to
program the FPGA. Once the FPGA is programmed with the correct design, you need to set up the
board according to the steps below:
1. Connect one end of the USB mini cable to USB port J2 on the M1AFS-ADV-DEV-KIT board
(labeled USB2 in Figure 2-9 ) and connect the other end to the USB port on your PC.
Figure 2-8 • HyperTerminal Window – Failed Message