SERIES PMC230 PCI MEZZANINE CARD 16-BIT HIGH-DENSITY ANALOG OUTPUT MODULE
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- 8 -
Most Significant Byte of Calibration Coefficient Access Reg
Read or
Write~
Calibration Coefficient Address
15
14, 13, 12, 11, 10, 9, 8
Write accesses to the Calibration Coefficient Access register
require one wait state and are possible via 16-bit data transfers only.
A software or hardware reset has no affect on this register.
The address location of each of the gain and offset coefficients
is given in table 3.4. The address corresponding to each of the
offset and gain coefficients for each of the channels and ranges is
given in hex. The coefficients are 16-bit values with the most
significant byte at the even addresses and the least significant bytes
at the odd addresses. The calibration coefficients are stored as 1/4
LSB’s. For additional details on the use of the calibration
coefficients, refer to the “Use of Calibration Data” section.
Table 3.4: Offset and Gain Address Memory Map
Channel
Offset Coefficient
Address (Hex)
Gain Coefficient
Address (Hex)
MSB LSB MSB LSB
0 00 01 02 03
1 04 05 06 07
±
10 2 08 09 0A 0B
Volt 3 0C 0D 0E 0F
Range
4 10 11 12 13
5 14 15 16 17
6 18
19
1A
1B
7
1C
1D
1E
1F
0 20 21 22 23
1 24 25 26 27
±
5 2 28 29 2A 2B
Volt 3 2C 2D 2E 2F
Range
4 30 31 32 33
5 34 35 36 37
6 38
39
3A
3B
7
3C
3D
3E
3F
0 40 41 42 43
1 44 45 46 47
0 to 10
2
48
49
4A
4B
Volt 3 4C 4D 4E 4F
Range
4 50 51 52 53
5 54 55 56 57
6 58
59
5A
5B
7
5C
5D
5E
5F
Calibration Coefficient Status Register (Read, 219H)
The Calibration Coefficient Status register is a read-only register
and is used to access the calibration coefficient read data and
determine the status of a read cycle initiated by the Calibration
Coefficient Access register. In addition, this register is used to
determine the status of a write cycle to the coefficient memory. Bit-1
of this register when set indicates the coefficient memory is busy
completing a write cycle.
All read accesses to the Calibration Coefficient Status register
initiate an approximately 1m second access to the coefficient
memory.
Thus, you must wait 1m second after reading this
status register before a new read or write cycle to the
coefficient memory can be initiated. If not you will get invalid
data.
A read request of the coefficient memory, initiated through the
Calibration Coefficient Access register, will provide the addressed
byte of the calibration coefficient on data bits 15 to 8 of the
Calibration Coefficient Status register. Although the read request via
the Calibration Coefficient Access register is accomplished in less
then 800n seconds, typically, the calibration coefficient will not be
available in the Calibration Coefficient Status register for
approximately 2.5m seconds.
Bit-0 of the Calibration Coefficient Status register is the read
complete status bit. This bit will be set high to indicate that the
requested calibration coefficient is available on data bits 15 to 8 of
this status register. This bit is cleared upon initiation of a new read
access of the coefficient memory or upon issue of a software or
hardware reset.
Writes to calibration coefficient memory require a special enable
code. Writes to coefficient memory are normally only performed at
the factory. The module should be returned to Acromag if
recalibration is needed.
A write operation to the calibration coefficient memory, initiated
via the Calibration Coefficient Access register, will take
approximately 5m seconds. Bit-1 of the Calibration Coefficient
Status register serves as a write operation busy status indicator. Bit-
1 will be set high upon initiation of a write operation, and bit-1 will
remain high until the requested write operation has completed. New
read or write accesses to the coefficient memory, via the Calibration
Coefficient Access register, should not be initiated unless the write
busy status bit-1 is clear (set low to 0). A software or hardware
reset of the PMC module will also clear this bit to 0.
Read accesses to Calibration Coefficient Status register require
one wait state and are possible via 16-bit data transfers only. A
software or hardware reset will clear all bits to 0.
Start Convert Register (Write Only, 21CH)
The Start Convert register is a write-only register and is used to
trigger conversions by setting data bit-0 to a logic one. The desired
mode of conversion must first be configured by setting the Control
register.
This register can be written with either a 16-bit or 8-bit data
value. Data bit-0 must be a logic one to initiate data conversions.
When External Trigger Only mode is selected via bits 6 and 5 of
the control register (set to “01”), the Software Start Convert bit is
disabled from starting data conversions.
Start Convert Register
Not Used
Start Convert
07 06 05 04 03 02 01
00
The actual conversion will be initiated 6.625
μ
seconds after
setting the Start Convert Bit. Thus in single conversion mode, you
cannot reload the DAC registers with new data until at least 6.625
μ
seconds after a start convert.
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