SERIES PMC230 PCI MEZZANINE CARD 16-BIT HIGH-DENSITY ANALOG OUTPUT MODULE
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- 10 -
written to the 16-bit DAC to achieve a specified voltage within the
selected output range.
Equation (1):
Ideal_ Count =
Count_ Span Desired_ Voltage
Ideal_ Volt_ Span
∗
⎡
⎣⎢
⎤
⎦⎥
where,
Count_Span
= 65,536 (a 16-bit converter has 2
16
possible levels)
Ideal_Volt_Span
= 20 Volts (for the bipolar -10 to +10 Volt range)
= 10 Volts (for the bipolar
±
5 or unipolar 0 to 10
volt
ranges).
Using equation (1), one can determine the ideal count for any
desired voltage within the range. For example, if it is desired to
output a voltage of +5 Volts for the bipolar
±
10 volt range, the
Ideal_Count of 16,384 results. If this value is used to program the
DAC output, the output value will ap5 Volts to within the
uncalibrated error. This will be acceptable for some applications.
For applications needing better accuracy, the software
calibration coefficients should be used to correct the Ideal_Count
into the Corrected_Count required to accurately produce the output
voltage. This is illustrated in the next equation.
Equation (2):
[
]
Corrected_ Count = Ideal_ Count
Gain_ Correction
Offset_ Correction
+ Ideal_ Zero_ Count
∗
+
+
1
where,
Gain_Correction =
Stored_Gain_Error / (4*65,536)
Offset_Correction =
Stored_Offset_Error / 4
Ideal_Zero_Count
= 0 for bipolar
±
5 and
±
10 volt ranges
-32,768 for unipolar 0 to 10 volt range
Ideal_Count is determined from equation (1) given above.
Stored_Gain_Error and Stored_Offset_Error are written at the
factory and are obtained from memory on the PMC230 on a per
channel basis. The Stored_Gain_Error and Stored_Offset_Error are
stored in memory as two’s complement numbers. Refer to the
“Calibration Coefficient Access Register” section for details on how
to read the coefficients from memory.
Using equation (2), you can determine the corrected count from
the ideal count. For the previous example, equation (1) returned a
result 16,384 for the Ideal_Count to produce an output of +5 Volts.
Assuming that a gain error of -185 and an offset error of -43 are
read from memory on the PMC230 for the desired channel,
substitution into equation (2) yields:
[
]
Corrected_ Count = 16,384
-
= 16,361.6875
∗
+
∗
−
1
185
4 65536
43
4
If this value (rounded to 16,362) is used to program the DAC
output, the output value will ap5 Volts to within the
calibrated error (see the specification chapter for details regarding
maximum calibrated error).
Calibration Programming Example
Assume it is necessary to program channel 0 with an output of
-2.5 Volts. Also assume the bipolar range centered around 0 Volts
is -10 to +10 Volts.
The Single Conversion from DAC Register mode of operation,
which is available on the PMC230 module, is used in this example.
1.
Execute Write of 0100H to Control Register at Base A
200H.
a)
External, Software, and Internal Hardware timer generated
triggers are all enabled.
b) Single Conversion from DAC registers is enabled.
2.
Read the calibration memory to retrieve channel 0’s unique
offset coefficient. To obtain the 16-bit offset coefficient, two
read accesses of the coefficient memory are required. To
initiate a read of channel 0’s most significant byte of the offset
coefficient, the Calibration Coefficient Access register must be
written with data value 8000H at Base A 214H. The
offset coefficient can be read by polling the Calibration
Coefficient Status register. When bit 0 of the Calibration
Coefficient Status register is set to logic high, then the data on
bits 15 to 8 contain the most significant byte of the offset
coefficient.
To initiate a read of channel 0’s least significant byte of the
offset coefficient, the Calibration Coefficient Access register
must be written with data value 8100H at Base A
214H. When bit 0 of the Calibration Coefficient Status register
is set to logic high, then the data on bits 15 to 8 of this register
contains the least significant byte of the offset coefficient.
3.
Read the calibration memory to retrieve channel 0’s unique 16-
bit gain coefficient. To obtain the 16-bit gain coefficient, two
read accesses of the coefficient memory are required. To
initiate a read of channel 0’s most significant byte of the gain
coefficient, the Calibration Coefficient Access register must be
written with data value 8200H at Base A 214H. The
gain coefficient can be read by polling the Calibration
Coefficient Status register. When bit 0 of the Calibration
Coefficient Status register is set to logic high, then the data on
bits 15 to 8 contains the most significant byte of the gain
coefficient.
To initiate a read of channel 0’s least significant byte of the gain
coefficient, the Calibration Coefficient Access register must be
written with data value 8300H at Base A 214H. When
bit 0 of the Calibration Coefficient Status register is set to logic
high, then the data on bits 15 to 8 of this register contains the
least significant byte of the gain coefficient.
4.
Calculate the Ideal_Count required to provide an uncorrected
output of the desired value (-2.5 Volts) by using equation (1).
Ideal_Count =
[65,536
×
(-2.5)]/20 = -8,192.0
5.
Calculate the Corrected_Count required to provide an accurate
output of the desired value (-2.5 Volts) by using equation (2).
Assume the offset and gain coefficients are -43 and -185
respectively.
Corrected_Count =
-8,192.0
×
[1 + -185/(4
×
65,536)] - 43/4 =
-8,196.9687. This value is rounded to -8,197 and is equivalent
to DFFB hex as a 2’s complement value.
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