SERIES PMC230 PCI MEZZANINE CARD 16-BIT HIGH-DENSITY ANALOG OUTPUT MODULE
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6.
Execute Write of DFFB hex to the DAC Channel 0 Register at
Base A 220H.
7.
Execute Write 0001H to the Start Convert Bit at Base Address
+ 21CH. This starts the simultaneous transfer of the digital
data in each DAC Channel register to its corresponding
converter for analog conversions. This will drive channel 0’s
analog output to -2.5 volts.
8.
(OPTIONAL) Observe or monitor that the specific DAC
channel (0) reflects the results of the digital data converted to
an analog output voltage at the field connector.
Error checking should be performed on the calculated count
values to insure that calculated values below 0 or above 65535
decimal are restricted to those end points. Note that the software
calibration cannot generate outputs near the endpoints of the range
which are clipped off due to hardware limitations(i.e. the DAC).
4.0 THEORY OF OPERATION
This section contains information regarding the hardware of the
PMC230. A description of the basic functionality of the circuitry
used on the board is also provided. Refer to the Block Diagram
shown in Drawing 4501-865 as you review this material.
FIELD ANALOG OUTPUTS
The field I/O interface to the PMC230 is provided through the
front panel connector P1 (refer to Table 2.3).
Field I/O signals are
NON-ISOLATED.
This means that the field return and logic
common have a direct electrical connection to each other. As such,
care must be taken to avoid ground loops (see Section 2 for
connection recommendations). Ignoring ground loops may cause
operation errors, and with extreme abuse, possible circuit damage.
Refer to Drawing 4501-864 for example wiring and grounding
connections.
Jumpers on the board control the range selection for the DACs
(-5 to +5, -10 to +10, and 0 to 10 Volts) as detailed in chapter 2.
Jumper selection should be made prior to powering the unit.
Channels may use different ranges.
PMC230 CONTROL LOGIC
All logic to control data conversions is imbedded in the PMC
module’s FPGA. The control logic of the PMC230 is responsible for
controlling the operation of a user specified mode of data
conversions. Once the PMC module has been configured, the
control logic performs the following:
•
Controls serial transfer of data from the FPGA to the
individual DAC registers based on the selected mode of
operation.
•
Provides external or internal trigger control.
•
Controls read and write access to calibration memory.
DATA TRANSFER FROM FPGA To INDIVIDUAL DACs
A 16-bit serial shift register is implemented in the PMC230
module’s FPGA for each of the supported channels. These serial
shift registers are referred to as the individual DAC registers in the
memory map. To control transfer of digital data to the individual
converters, internal FPGA counters are used to synchronize the
simultaneous transfer of serial shift register data to the
corresponding converter.
The DACs can be updated with new digital values or left
unchanged. The DACs are updated by first writing the individual
DAC registers, resident in the FPGA. Then, upon issue of a trigger
(software or external), the contents of the DAC registers are
simultaneously transferred to the DACs.
EXTERNAL TRIGGER
The external trigger connection is made via pin 49 of the P1
Field I/O Connector. For all modes of operation, when external
trigger input is enabled via bits 6 and 5 of the control register, the
falling edge of the external trigger will start the simultaneous
conversion of all channels. For External Trigger Only mode (bits 6
and 5 set to “01”), each falling edge of the external trigger causes a
conversion at the DAC. Once the external trigger signal has been
driven low, it should remain low for a minimum of 125n seconds and
a maximum of 6
μ
seconds, or additional unwanted conversions may
be triggered.
CALIBRATION MEMORY CONTROL LOGIC
The FPGAs of the PMC230 modules contain control logic that
implements read and write access to calibration memory. The
calibration memory (EEPROM) contains offset and gain coefficients
for each of the ranges and channels. Calibration of the individual
DACs is implemented via software to avoid the mechanical
drawbacks of hardware potentiometers.
PCI INTERFACE LOGIC
The PCI bus interface logic is imbedded within an FPGA. This
logic includes support for PCI commands, including: configuration
read/write, and memory read/write. In addition, the PCI target
interface performs parity error detection, uses a single 4K base
address register, and implements target abort, retry, and disconnect.
J1 and J2 connectors also provide
±
12V and +5V to power the
module.
A PCI bus read of the PMC module will initially terminate with a
retry. While the read data is moved to the read register (typically
1000ns), continued retries will result in retry terminations. The retry
termination allows the PCI bus to be free for other system
operations while the data is moved to the read register.
A PCI bus write to the PMC module will result in 1)
immmediately accepting the write data and normal cycle termination
or 2) issue of a retry termination. A retry termination will be issued if
the previous write cycle has not completed on the PMC module. It
will typically take the PMC module 1000ns to write the data to the
required internal register. Thus if another write cycle is initiated on
the PCI bus before the typical 1000ns has lapsed, the write cycle will
be terminated with a retry.
A programmable logic device provides the control signals
required to operate the board. It decodes the selected addresses
and produces the chip selects, control signals, timing required by
the DAC’s, and software registers. It also controls the mode
selection and triggering to start DAC conversions for the
Transparent and Simultaneous Modes.
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