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SERIES  I/O SERVER MODULE

 

MIL-STD-1553A/B Bus Interface Module 

________________________________________________________________________

 

 

 

 

Acromag, Inc. Tel:248-295-0310  Fax:248-624-9234     Email:[email protected]  

www.acromag.com 

Table 4 IOS-57x ID ROM 

Hex 

Offset 

From ID 

PROM 

Base 

Address 

 

ASCII 

Character  

Equivalent 

 

Numeric 

 Value 

 (Hex) 

 
 
 

Field Description 

00 

49 

Format I ID ROM  supports 8 or 32 MHz IOS 
bus clock frequency 

02 

50 

 

04 

41 

 

06 

48 

 

08 

 

A3 

Acromag ID Code 

0A 

 

 

IOS Model Code

1

  

52 

IOS-571 

53 

IOS-572 

0C 

 

00 

Not Used (Revision) 

0E 

 

00 

Reserved 

10 

 

00 

Not Used (Driver ID Low Byte) 

12 

 

00 

Not Used (Driver ID High Byte) 

14 

 

0C 

Total Number of ID PROM Bytes 

16 

 

 

CRC 

8F 

IOS-571 

EE 

IOS-572 

18 to 3E 

 

yy 

Not Used 

Note (Table 4): 

1.  The model number is represented by a two-digit code within the ID space (the 

IOS-571 model is represented by 52H, the IOS-572 is represented by 53H). 

ADDRESS MAP 

Table 5 IOS-57x Address Map 

Description 

IOS Address 

Space 

Access Type 

Address Offset from 

base 

Control Register  

I/O 

16 bit only 

Status Register 

I/O 

16 bit only 

Channel 0 Interrupt Vector   I/O 

8 bit 

Channel 1 Interrupt Vector   I/O 

8 bit 

ID ROM 

ID 

8 bit 

0x00 

– 0x16 

Channel 0 uACE registers 

Memory 

16 bit only 

0x00000 

– 0x0003E 

Channel 0 uACE RAM 

Memory 

16 bit only 

0x20000 

– 0x3FFFE 

Channel 1 uACE registers 

Memory 

16 bit only 

0x40000 

– 0x4003E 

Channel 1 uACE RAM 

Memory 

16 bit only 

0x60000 

– 0x7FFFE 

 

I/O SPACE ADDRESS MAP 

I/O address space is used to provide access to control registers, a status register, and 
interrupt vector registers.   

Summary of Contents for IOS-571

Page 1: ...rface Module USER S MANUAL ACROMAG INCORPORATED Tel 248 295 0310 30765 South Wixom Road Fax 248 624 9234 P O BOX 437 Wixom MI 48393 7037 U S A solutions acromag com Copyright 2010 2011 Acromag Inc Pri...

Page 2: ...UNPACKING AND INSPECTION 6 INSTALLATION 6 CONNECTORS 6 Field I O Connector P2 6 CABLE 7 Non Isolation Considerations 8 PROGRAMMING INFORMATION 8 IDENTIFICATION PROM 8 ADDRESS MAP 9 I O SPACE ADDRESS M...

Page 3: ...PUBLICATIONS The following manuals and part specifications provide the necessary information for in depth understanding of the IOS 57x Series boards These documents are available on the Data Device C...

Page 4: ...les may be installed in an I O Server if all channels are operating in monitor mode transmitter duty cycle is 0 KEY FEATURES One or two dual redundant MIL STD 1553A B channels Each channel can be inde...

Page 5: ...e DLL functions provide a high level interface to boards eliminating the need to perform low level reads writes of registers and the writing of interrupt handlers I O SERVER Linux SOFTWARE Acromag pro...

Page 6: ...le shipping cartons and packing material be saved for future use in the event the product must be shipped This board is physically protected with packing material and electrically protected with an an...

Page 7: ...CK_IN 8 GND 33 GND 9 GND 34 GND 10 CH1B_DIRECT_N 35 CH1B_XFMR_N 11 CH1B_DIRECT_P 36 CH1B_XFMR_P 12 GND 37 GND 13 GND 38 GND 14 CH1A_DIRECT_N 39 CH1A_XFMR_N 15 CH1A_DIRECT_P 40 CH1A_XFMR_P 16 GND 41 GN...

Page 8: ...connections PROGRAMMING INFORMATION This Section provides the specific information necessary to program and operate the board IDENTIFICATION PROM Each IOS module contains identification ID information...

Page 9: ...CRC 8F IOS 571 EE IOS 572 18 to 3E yy Not Used Note Table 4 1 The model number is represented by a two digit code within the ID space the IOS 571 model is represented by 52H the IOS 572 is represente...

Page 10: ...it A 0 4 Channel 0 Transceiver Inhibit B 0 3 Channel 0 Master Clear 0 2 Channel 0 Built In Self Test Enable 0 1 Channel 0 Remote Terminal Address Latch 0 0 Channel 0 Interrupt Enable 0 IOS bus clock A...

Page 11: ...is connected to IRQ0 Channel 1 interrupt is connected to IRQ1 MEMORY SPACE ADDRESS MAP This board is addressable in memory space to access the Micro ACE 1553 controllers The IOS 571 uses the lower 256...

Page 12: ...er 5 RD WR 00014 RT Monitor Data Stack Address Register RD 00016 BC Frame Time Remaining Register RD 00018 BC Time Remaining to Next Message Register RD 0001A Non Enhanced BC Frame Time Enhanced BC In...

Page 13: ...gister 2 to select LEVEL type interrupt signaling for each channel This will enable the FPGA to pass the Micro ACE interrupt signal through to the IOS bus INTREQx interrupt See the Enhanced Mini ACE S...

Page 14: ...IC All logic to provide access to the Micro ACE 1553 controllers is imbedded in the module s FPGA Once the IOS 57x FPGA has been configured the control logic provides the following functions Source of...

Page 15: ...its and the RT parity bit must be odd The RT address may be latched in the Micro ACE The RT address latch signal is controlled by the IOS I O control register Bit 9 controls the RT address latch signa...

Page 16: ...eded complete repair services are also available from Acromag WHERE TO GET HELP If you continue to have problems your next step should be to visit the Acromag worldwide web site at http www acromag co...

Page 17: ...EN50082 1 Electric Fast Transient Immunity EFT Complies IEC 6100 4 4 2007 Electrostatic Discharge ESD Immunity Complies with IEC 61000 4 2 2001 8KV enclosure port air discharge Level 3 4KV enclosure...

Page 18: ...x Unit CHx_RT_ADDRx CHx_RT_PARITY VIL low level input voltage 0 6 V VIH high level input voltage 2 0 3 3 V IIL low level current VIL 0 V 330 A TAG_CLK_IN VIL low level input voltage 0 8 V VIH high lev...

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