SERIES I/O SERVER MODULE
MIL-STD-1553A/B Bus Interface Module
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Acromag, Inc. Tel:248-295-0310 Fax:248-624-9234 Email:[email protected]
www.acromag.com
The I/O space may be as large as 64, 16-bit words (128 bytes) using address lines A1 to
A6, but the IOS-57x uses only a portion of this space. The I/O space address map for the
IOS-57x is shown in Table 5. Note that the base address for the IOS module I/O space
(see your carrier board instructions) must be added to the addresses shown to properly
access the I/O space.
Table 6 Control Register Read / Write I/O base a 0
Bit
Description
Reset State
15 - 14
IOS bus clock
0
13
Channel 1 Transceiver Inhibit A
0
12
Channel 1 Transceiver Inhibit B
0
11
Channel 1 Master Clear
0
10
Channel 1 Built In Self Test Enable
0
9
Channel 1 Remote Terminal Address Latch
0
8
Channel 1 Interrupt Enable
0
7
Tag Clock Source
0
6
Not used
0
5
Channel 0 Transceiver Inhibit A
0
4
Channel 0 Transceiver Inhibit B
0
3
Channel 0 Master Clear
0
2
Channel 0 Built In Self Test Enable
0
1
Channel 0 Remote Terminal Address Latch
0
0
Channel 0 Interrupt Enable
0
IOS bus clock
: A phase locked loop is used to generate the module clock from the IOS
bus clock. The IOS bus clock must remain constant after setting the appropriate bits in this
register. The module clock is not enabled until the IOS bus clock frequency is specified by
writing the following bit pattern:
00
– module clock disabled
01
– IOS bus clock 8 MHz, enable module clock
10
– IOS bus clock 32 MHz, enable module clock
11
– module clock disabled
Transceiver Inhibit A
:
0 - transceiver enable
1
– transceiver disabled
Transceiver Inhibit B
:
0 - transceiver enable
1
– transceiver disabled
Master Clear
: is a write only bit, always reads as 0
0
– normal operation
1
– hardware reset
Built In Self Test Enable:
0
– disables both the power up and user initiated built in self test
1
– built in self test will be enabled after hardware reset
Remote Terminal Address Latch
: controls
the μ-ACE's internal RT address latch. (see μ-
ACE hardware manual for further description)
Interrupt enable
:
0
– interrupts disabled
1
– interrupts enabled
