75
Chapter 4
E5
DEBUG_PCI_ADDIN_ROM_
DISABLE_2
disable PCI video device add-in rom card decode
E6
DEBUG_RET_PCI_2
PCI device config finish
E7
DEBUG_BRIDGE_HUNT
Search for PCI bridge controllor device
E8
DEBUG_PCI_IDE_FIND
Search IDE controllors on the PCI bus, and
config the IDE controllors
E9
DEBUG_CB_CONFIG
start of cardbus config
PNP BIOS -- PNPINIT.ASM
A1
DEBUG_PNP_ENABLE_VERIFY_RT
DATA
Enable and Verify R/W Status for PNP BIOS
Runtime Data Area
A2
DEBUG_PNP_GET_VERIFY_NVRAM Get and Verify R/W Status for PNP BIOS
NVRAM data area
A3
DEBUG_PNP_SYSTEM_NODES
Resolve System Nodes with the CMOS settings
A4
DEBUG_PNP_INITIALIZE_RTDATA
Initialize variable in the PNP BIOS Runtime Data
area
A5
DEBUG_PNP_HOOK_INT15
Hook INT 15
A6
DEBUG_PNP_SET_COPY_AREA
copy and setup PnP BIOS sytem node
A7
DEBUG_PNP_OEM_LATE_HOOK
Allow the OEM any Last Minute Hooks
A8
DEBUG_PNP_WRITE_PROTECT_R
T_DAT
Write protect RTData Area and NVRAM Copy
Buffer, and make runtime data checksum
A9
DEBUG_PNP_INIT_RETURN
PNP BIOS initialize finish
General SMI Entry/Exit Code -- SMICHIP.ASM
C0
dSMI_ENTRY
SMI procedure entry point
C1
dSMI_EXIT
SMI procedure exit
C2
dSMI_APM_ENTRY
APM MODE SMI procedure entry point
C3
dSMI_APM_EXIT
APM MODE SMI procedure exit
Software SMI request Codes -- SWSHELL.ASM
C4
dSMI_SWEXEFN
SoftWare SMI function execution
C5
dSMI_HWEXEFN
HardWare SMI function execution
POST Code
Macro Name
Description
Summary of Contents for Aspire 9100 Series
Page 36: ...Chapter 1 29 ...
Page 46: ...39 Chapter 2 ...
Page 53: ...Chapter 3 46 ...
Page 58: ...51 Chapter 3 ...
Page 65: ...Chapter 3 58 ...
Page 66: ...59 Chapter 3 ...
Page 88: ...81 Chapter 4 ...
Page 92: ...85 Chapter 6 Aspire 9100 Exploded Diagram ...
Page 108: ...101 Appendix C ...
Page 111: ...Index 104 ...