Chapter 1
3
System Block Diagram
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
Title
Si
ze
D
a
te
:
S
heet
of
System Block Diagram
25
8
妨茗
,
27, 2004
Acer Inc.
D
o
than
Inte
rnal LVDS
CRT
Signal
PCI-E 16X
A
T
I M
24P
CRT CONN
p
age 25
T
V
OUT
LVDS CONN
p
age 24
+
1.5VS
+
2.5V
+
VCCP
+3VS
Clock Ge
nerator
H_A#(3..31)
H_D#(0
..6
3
)
DM
I
INTEL
P
entium-M
page 9,10,11,12,13
p
age 17
p
a
ge 5,6,7
M
o
del :
AS9100
System B
us
2.5
V
333
MHz
+
1.5VS
100MHz
+
V
C
CP 400/533 MHz
M
emory BUS
(DDR
I)
1
257BGA
p
age 8
IC
S954226
p
age 25
478p
i
n
u
F
CPGA CPU
+5VS
+
V
CCP (1.05V)
+
CPU_CORE
+3VS
DDR
I-
DIMM X
2
p
a
ge 14,15
BANK 0, 1, 2,
3
+2.
5
V
S
page
8
G7
8
1
Therm
al(CPU)
+3VS
FA
N
page 18,19,20,21
Alvis
o
+3VS
+3V
+
1.5VS
+
1.5V
+
2.5VS
609 BGA
INTEL
page 27,28,29,30
ICH6
-M
+3
V
S
+
5VAMP
+
5VAMP
+
5VALW
RJ11
p
age 45
HeadPho
n
e &
MIC C
O
N
N
+3V
USB Ports
X4
AMP
& IN
T.
S
p
eaker
p
age 40
AC97 Co
de
c
p
age 44
48MH
z
24
.5
76MHz
A
T
A100
MDC
p
age 39
A
L
C250
A
C-LINK
p
age 45
+
5VAMP
Cab
l
e
USB[
0,2,4,6]
+5VS
+3VS
+
3VALW
+5VS
P
o
rt DEBUG
p
age 43
LP
C
B
U
S
p
age 41
+
3
VAL
W
33MH
z
K
B
910
X B
U
S
p
age 43
Touch Pa
d
&
LID S
W
Int.KBD
p
age 43
R
T
C BATT
p
age 50
P
o
w
er
On/Off
SW &
LED
p
age 43
p
age 47
DC/DC Inter
fa
ce
CPU_CORE
+1.5VS/+VC
C
P
p
age 55
p
age 53
p
age 49
CHA
RGER
+1.
8
V
S
/
+VGA_CO
R
E
p
age 54
2.5V/+1.2VS
/
+
1
.25VS
p
age 52
p
age 48
DC
IN
3V
/5
V/12V
F
rame Buffer
p
a
ge 22,23
6
4/128
SST39VF
0
4
0
P
ar
a
llel ATA
p
age 31
+5VS
IDE
+
5VCD
CD-ROM
p
age 31
IDSEL:AD2
0
(PIRQA,B#,GNT#2,REQ#2
),SIRQ
CardBus Controller
ENE CB7
1
2
p
age 33
Ca
rd
Reade
r
IDSEL:AD1
6
(PIRQE#,GNT#0,RE
Q#0)
p
age 34
1
394 Controller
PCMC
IA
Slot
p
age 35
RJ45
p
age 36
R
T
L
8110SBL
/8
100CL
WIREL
E
S
S
TV Turn
er
PCI
BU
S
+3VAL
W 3
3M
H
z
Minipci CON
N
X
2
p
a
ge 37,38
IDSEL:AD1
9
(PIRQH#,PIRQG#,GNT#4,
REQ#4)
p
age 34
13
9
4
CONN
+
3VALW
IDSEL:AD1
7
(PIRQF#,GNT#3,RE
Q#3)
p
age 32
p
age 33
+
1.5VS
+
1.8VS
+
VGA_CORE
+3VS
+2.
5
V
S
+
1.25VS
+
2.5V
+1.
2
V
S
G
781-1
page 26
Therm
al(VGA)
+3VS
V
T
6301S
IDSEL:AD1
8
(PIRQG#,PIRQH#,GNT#1,
REQ#1)
p
age 51
p
age 42
p
age 36
+3
V
S
+5
V
S
+5
V
S
+
S
1
_VCC
+3
V
S
+
V
C
C_5IN1
+
S
1
_VCC
+
S
1
_VPP
+3
V
S
Summary of Contents for Aspire 9100 Series
Page 36: ...Chapter 1 29 ...
Page 46: ...39 Chapter 2 ...
Page 53: ...Chapter 3 46 ...
Page 58: ...51 Chapter 3 ...
Page 65: ...Chapter 3 58 ...
Page 66: ...59 Chapter 3 ...
Page 88: ...81 Chapter 4 ...
Page 92: ...85 Chapter 6 Aspire 9100 Exploded Diagram ...
Page 108: ...101 Appendix C ...
Page 111: ...Index 104 ...