Abov AC30M1x32 User Manual Download Page 133

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ABOV Semiconductor

FRT

FRT.PER

FRT Period Match Register

8.2.3

FRT Period Match Register is 32-bit register

FRT.PER=0x4000_0608

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

PERIOD

0x0000_0000

32
0

PERIOD

FRT Period Match Data

FRT.CNT

FRT Counter Register

8.2.4

FRT Counter Register is 32-bit register

FRT.CNT=0x4000_060C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

CNT

0x0000_0000

32
0

CNT

FRT Counter

FRT.SR

FRT Status Register

8.2.5

FRT Status Register is 8-bit register.

FRT.SR=0x4000_0610

RACK

OVF

WC1

RACK

Read Counter Acknowledge bit
0

Not ready to read CNT value

Ready to read CNT value

OVF

OverFlow Interrupt flag bit
0

Overflow interrupt did not occur

Overflow interrupt occurred

Interrupt flag bit
0

Match interrupt did not occur.

Match Interrupt occurred
In Counter Match Clear mode, this bit should be cleared

for restarting the counter.

Summary of Contents for AC30M1x32

Page 1: ...32 bit Cortex M0 based Programmable Motor Controller FlashROM 64 32KB SRAM 4KB AC30M1x64 AC30M1x32 USER MANUAL Version 1 1 0 2016 8 17 ...

Page 2: ...pment communication equipment measuring equipment domestic electrification etc Please make sure that you consult with us before you use these ABOV Semiconductor products in equipment which require high quality and or reliability and in equipment which could have major impact to the welfare of human life atomic energy control airplane spaceship traffic signal combustion control all types of safety ...

Page 3: ...3 246 ABOV Semiconductor INTRODUCTION SECTION 1 INTRODUCTION ...

Page 4: ...4 246 4 246 AC30M1x64 1x32 ABOV Semiconductor OVERVIEW CHAPTER 1 ...

Page 5: ...rom motor It can control up to one inverter motor Powerful and various external serial interfaces help to communicate with on board sensors and devices AC30M1x64 1x32 Block Diagram Advanced High Performance Bus AHB Advanced Peripheral Bus APB Core and Memory System Control Units Serial Interfaces I O Ports Timers Analog Interfaces ARM Cortex M0 Processor Up to 40MHz Code Flash 64 32KB SWD Debug In...

Page 6: ...PA14 T2IO PA13 T1IO PA12 T0IO PC8 SDA PC7 SCL T3IO PC1 SWDIO TXD1 PC0 SWCLK RXD1 VDD PC2 PC3 PC9 CLKO PC11 T0IO BOOT PC15 TXD0 PC14 RXD0 GND AN8 T2IO T0IO PA8 AN9 T1IO T3IO PA9 AN10 PA10 AN11 PA11 nRESET PC10 AVDD VDD AGND GND XOUT T2IO PC13 XIN T3IO PC12 SXIN SDA MISO PD3 SXOUT SCL MOSI PD2 SCK PD1 SS PD0 T0IO PC4 T1IO RXD1 PC5 T2IO TXD1 PC6 OVIN PB7 PRTIN PB6 MPWMWL PB5 MPWMWH PB4 MISO MPWMVL PB...

Page 7: ...IO AN1 PA0 T2IO AN0 PC8 SDA PC7 SCL T3IO PC1 SWDIO TXD1 PC0 SWCLK RXD1 PC11 T0IO BOOT PC14 RXD0 PB0 MPWMUH SS PB1 MPWMUL SCK PC15 TXD0 AN8 T2IO T0IO PA8 AN9 T1IO T3IO PA9 nRESET PC10 AVDD VDD AGND GND XOUT T2IO PC13 XIN T3IO PC12 SXIN SDA MISO PD3 SXOUT SCL MOSI PD2 OVIN PB7 PRTIN PB6 MPWMWL PB5 MPWMWH PB4 MISO MPWMVL PB3 MOSI MPWMVH PB2 AC30M1364LBN AC30M1332LBN LQFP 32 Figure 1 3 PIN LAYOUT LQFP...

Page 8: ...2 PA1 T3IO AN1 PA0 T2IO AN0 PC8 SDA PC7 SCL T3IO PC1 SWDIO TXD1 PC0 SWCLK RXD1 PC11 T0IO BOOT PC14 RXD0 PB0 MPWMUH SS PB1 MPWMUL SCK PC15 TXD0 AN8 T2IO T0IO PA8 AN9 T1IO T3IO PA9 nRESET PC10 AVDD VDD AGND GND XOUT T2IO PC13 XIN T3IO PC12 SXIN SDA MISO PD3 SXOUT SCL MOSI PD2 OVIN PB7 PRTIN PB6 MPWMWL PB5 MPWMWH PB4 MISO MPWMVL PB3 MOSI MPWMVH PB2 AC30M1364UB AC30M1332UB QFN 32 Figure 1 4 PIN LAYOUT...

Page 9: ...in 10 ch 32 Pin Timer 16 Bit 4 ch Free Run Timer 32 Bit 1 ch Watchdog Timer 32 Bit 1 ch External communication ports 2 ch UARTs 1 ch I 2 C 1 ch SPI Hardware Divider DIV64 On Chip RC Oscillator HSI 40MHz 3 40 105 LSI 40kHz 20 40 105 System Fail Safe function by Clock Monitoring XTAL OSC Fail monitoring Power On Reset Programmable Low Voltage Detector Brown Out Detector Debug and Emergency stop func...

Page 10: ...M UART SPI I2C MPWM ADC I O Ports Package AC30M1464LBN 64KB 4KB 2 1 1 1 1 unit 12 ch 44 LQFP 48 AC30M1364LBN 64KB 4KB 2 1 1 1 1 unit 10 ch 30 LQFP 32 AC30M1364UB 64KB 4KB 2 1 1 1 1 unit 10 ch 30 QFN 32 AC30M1332LBN 32KB 4KB 2 1 1 1 1 unit 10 ch 30 LQFP 32 AC30M1332UB 32KB 4KB 2 1 1 1 1 unit 10 ch 30 QFN 32 ...

Page 11: ...A D Converter CRC CCITT UART0 UART1 I2C HSI 40MHz LSI 40kHz Clock Control MOSC 4 16MHz SOSC 32 768kHz SPI Watch Dog Timer Free Run Timer 16 Bit Timer 0 16 Bit Timer 1 16 Bit Timer 2 16 Bit Timer 3 MPWM Port A Port B Port C Port D VDD VSS nRESET BOOT SWCLK SWDIO XIN XOUT SUB XIN SUB XOUT VDD AIN0 AIN11 VSS RX0 TX0 RX1 TX1 SCL SDA MOSI MISO SCK SS MPWMUH MPWMUL MPWMVH MPWMVL MPWMWH MPWMWL T0IO T1IO ...

Page 12: ...to be performed without the overhead of state saving and restoring 64 32KB Internal Code Flash Memory The AC30M1x64 1x32 provides internal 64 32KB code flash memory and its controller This is enough to program motor algorithm and general control the system Self programming is available and ISP and SWD programming is also supported in boot or debugging mode Instruction and data cache buffer are pre...

Page 13: ...unication The master and the slave mode are supported Universal Asynchronous Receiver Transmitter UART The AC30M1x64 1x32 has 2 channels UART block For accurate baud rate control the fractional baud rate generator is provided General PORT I Os 16 bit PA 8 bit PB 16 bit PC and 4 bit PD ports are available and provide multiple functionality General I O port Independent bit set clear function Externa...

Page 14: ...tection Input signal 7 5 PB5 IOUS PORT B Bit 5 Input Output MPWMWL O MPWM WL Output 8 6 PB4 IOUS PORT B Bit 4 Input Output MPWMWH O MPWM WH Output 9 7 PB3 IOUS PORT B Bit 3 Input Output MPWMVL O MPWM VL Output MISO I O SPI Channel Master In Slave Out 10 8 PB2 IOUS PORT B Bit 2 Input Output MPWMVH O MPWM VH Output MOSI I O SPI Channel Master Out Slave In 11 9 PB1 IOUS PORT B Bit 1 Input Output MPWM...

Page 15: ...put AIN1 IA Analog Input 1 31 20 PA2 IOUS PORT A Bit 2 Input Output SS I O SPI Channel Slave Select In Out WDTO O Watchdog Timer Overflow Output AIN2 IA Analog Input 2 32 21 PA3 IOUS PORT A Bit 3 Input Output SCK I O SPI Channel CLK In Out STBO O Power Down Mode Output AIN3 IA Analog Input 3 33 22 PA4 IOUS PORT A Bit 4 Input Output AIN4 IA Analog Input 4 34 23 PA5 IOUS PORT A Bit 5 Input Output AI...

Page 16: ...ystal Oscillator Input 46 1 PD3 IOUS PORT D Bit 3 Input Output MISO I O SPI Channel Master In Slave Out SDA I O I 2 C Channel SDA In Out SXIN I External Crystal Sub Oscillator Input 47 2 PD2 IOUS PORT D Bit 2 Input Output MOSI I O SPI Channel Master Out Slave In SCL I O I 2 C Channel SCL In Out SXOUT OA External Crystal Sub Oscillator Output 48 PD1 IOUS PORT D Bit 1 Input Output SCK I O SPI Clock ...

Page 17: ... I2C ADC 0x4000 C000 0x0000 0000 MIRROR CODE 0x2000 0000 0x4000 0000 0x6000 0000 0x8000 0000 0xA000 0000 0xC000 0000 0xE000 0000 0xFFFF FFFF SRAM 4KB Peripherals Reserved Cortex M0 Peripherals 0xE010 0000 0x0000 0000 CODE 0x0F00 0000 0x1FFF 0000 0x1FFF FFFF SRAM BOOT ROM 2KB FLASH ROM 64 32KB 0x0001 0000 OTP 0x0F00 0600 0x1FFF 0800 0x3000 0000 CODE 0x3E00 0000 0x3FFF FFFF SRAM OTP MIRROR FLASH ROM...

Page 18: ...18 246 18 246 ABOV Semiconductor AC30M1x64 1x32 CPU CHAPTER 2 ...

Page 19: ... Semiconductor CPU Cortex M0 Core 2 1 CPU core is supported from the ARM Cortex M0 processor which provides a high performance low cost platform Document DDI0432C from ARM provides detail information of Cortex M0 ...

Page 20: ...0000_002C SVCall Handler 4 0x0000_0030 Debug Monitor Handler 3 0x0000_0034 Reserved 2 0x0000_0038 PenSV Handler 1 0x0000_003C SysTick Handler 0 0x0000_0040 LVDFAIL 1 0x0000_0044 SYSCLKFAIL 2 0x0000_0048 MOSCFAIL 3 0x0000_004C SOSCFAIL 4 0x0000_0050 WDT 5 0x0000_0054 TIMER0 6 0x0000_0058 TIMER1 7 0x0000_005C TIMER2 8 0x0000_0060 TIMER3 9 0x0000_0064 FRT 10 0x0000_0068 GPIOAE 11 0x0000_006C GPIOAO 1...

Page 21: ...nterrupt has an associated priority level register Each of them is 2 bits wide occupying the two MSBs of the Interrupt Priority Level Registers Each Interrupt Priority Level Register occupies 1 byte 8 bits NVIC registers in the Cortex M0 processor can only be accessed using word size transfers so for each access four Interrupt Priority Level Registers are accessed at the same time __NVIC_PRIO_BITS...

Page 22: ...22 246 22 246 ABOV Semiconductor AC30M1x64 1x32 Boot Mode CHAPTER 3 ...

Page 23: ...nd SPI boot UART boot uses UART0 port and SPI boot uses SPI The pins for boot mode are listed as following Table3 1 Boot mode pin list Block Pin Name Dir Description SYSTEM nRESET PC10 I Reset Input signal BOOT PC11 I 0 to enter Boot mode UART0 RXD0 PC14 I UART Boot Receive Data TXD0 PC15 O UART Boot Transmit Data SPI SS PA2 I SPI Boot Slave Select SCK PA3 I SPI Boot Clock Input MOSI PD2 I SPI Boo...

Page 24: ...Followings are sample connection diagrams of boot mode AC30M1x64 AC30M1x32 VDD nRESET BOOT RXD0 TXD0 GND RESET BOOT HOST TXD RXD GND VDD 2 2 5 5V 10kΩ Figure 3 1 Connection diagram of UART Boot AC30M1x64 AC30M1x32 VDD nRESET BOOT SS SCK MOSI MISO GND RESET BOOT HOST SCK SS SDO SDI GND VDD 2 2 5 5V 10kΩ Figure 3 2 Connection diagram of SPI Boot ...

Page 25: ...OT MODE ISP Mode Connections 3 3 User can design target board using any of ISP mode port AC30M1x64 AC30M1x32 VDD nRESET SWCLK SWDIO GND nRESET E PGM SWCLK SWDIO GND VDD 2 2 5 5V 10kΩ Figure 3 3 Connection diagram of ISP and E PGM ...

Page 26: ...26 246 26 246 ABOV Semiconductor AC30M1x64 1x32 SECTION 2 PERIPHERALS ...

Page 27: ...27 246 ABOV Semiconductor System Control Unit SCU SYSTEM CONTROL UNIT SCU CHAPTER 1 ...

Page 28: ...log blocks and operating modes Internal reset and clock signals are controlled by SCU block to maintain optimize system performance and power dissipation SCU MODE CONTROL SCU CLOCK GENERATOR POWER DOWN WAKE UP VDC LVD BOD OSC CONTROL RESET INTERRUPT INTERRUPT APB BUS SCU HCLK MCLK PCLK_A B WAKE UP SOURCE VDC LVD BOD OSC Figure 1 1 SCU Block Diagram ...

Page 29: ...CR3 SCU MCCR3 SCU MCCR4 5 SCU MCCR7 SCU MCCR7 MCCRn CLK SCU SCCR 1 0 SCU SCCR 1 0 SCU SCCR 2 SCU MCCRn DIV Power down Mode Power down Mode CM0 Power down Mode Sleep Mode FCLK HCLK MCLK SCU CSCR 4 SCU CSCR 6 SCU CSCR 0 SCU CSCR 3 SCU PCER1 2 SCU CSCR 7 SCU CSCR 1 SCU CSCR 2 SCU MCCRn CSEL MCLK 7 0 2 0 MEM BUS PCLK_B Power down Mode SCU CSCR 5 SCU SMR 9 Power down Mode SOSC CLK LSI CLK MOSC CLK HSI ...

Page 30: ...efault system clock is feed by LSI 40kHz clock LSI is default enabled at power up sequence The other clock sources will be enabled by user controls with the LSI system clock HSI 40MHz clock can be enabled by SCU CSCR register MOSC 4 16MHz clock can be enabled by SCU CSCR register Before enable MOSC block the pin mux configuration should be set for XIN XOUT function PC12 and PC13 pins are shared wi...

Page 31: ...SCU SCCR SOSC SCU SCCR HSI MOSC 4 16MHz SOSC 32 768KHz HSI 40MHz SCU CSCR 0xXX Disable unused clock source SCU CSCR Enable All Clock Y Y Y N N N Figure 1 3 Clock change procedure When you speed up the system clock until max operating frequency you should check flash wait control configuration Flash read access time is one of limitation factor for the performance The wait control recommendation is ...

Page 32: ... the system boot Internal VDC is enabled when VDDEXT power is turn on Internal POR trigger level is 1 4V of VDDEXT voltage out level At this time boot operation is started The LSI clock is enabled and counts 4 25msec time for internal VDC level stabilizing In this time VDDEXT voltage level should be over than initial LVD level 1 65V After 4 25msec counting the cold reset is released and counts 0 4...

Page 33: ...occurred The warm reset source is controlled by SCU RSER register and the status is appeared in SCU RSSR register The reset for each peripheral blocks is controlled by SCU PRER register The reset can be masked independently PIN_RSTB WARM_RSTB_CNT WARM_RSTB 0 4 msec SYS_RSTB BOOTROM EXCUTION 42 1 msec MAIN CODE START 0 4 msec 42 5msec Typical Typical Typical Typical Figure 1 5 Warm reset diagram ...

Page 34: ... 1 b1 SCU PRER1 2 WDT RESETn 1 b1 SCU PRER1 3 PCU RESETn SCU PER1 4 SCU PRER1 5 DIV RESETn SCU PER1 8 SCU PRER1 8 GPIOA RESETn SCU PER1 9 SCU PRER1 9 GPIOB RESETn SCU PER1 10 SCU PRER1 10 GPIOC RESETn SCU PER1 11 SCU PRER1 11 GPIOD RESETn SCU PER1 16 SCU PRER1 16 TIMER0 RESETn SCU PER1 17 SCU PRER1 17 TIMER1 RESETn SCU PER1 18 SCU PRER1 18 TIMER2 RESETn SCU PER1 19 SCU PRER1 19 TIMER3 RESETn SCU P...

Page 35: ...e used as the low power consumption mode The low power consumption is achieved by halting processor core and unused peripherals Figure 1 7 shows the operation mode transition diagram INIT RUN SLEEP POWER DOWN WAKE UP EVENT PCU WAKE UP EVENT WFI SCB SCR 2 0 WFI SCB SCR 2 1 MCU INITIALIZATION RESET EVENT RESET EVENT RESET EVENT POWER ON RESET note SCB SCR is System Control Register in System Control...

Page 36: ...36 246 AC30M1x64 1x32 ABOV Semiconductor RUN Mode 1 3 5 This mode is to operate the CPU and the peripheral hardware by using the high speed clock After reset followed by INIT state it is entered into RUN mode ...

Page 37: ...mode Each peripheral function can be enabled by the function enable and clock enable bit in the PER and PCER register SLEEP MODE ENTER END WFI ENTER SLEEP MODE Wait for Interrupt signal WAKE UP SCB SCR 2 0 note SCB SCR is System Control Register in System Control Block Figure 1 8 Sleep mode sequence ...

Page 38: ...0 TRIM MODE SCU VDCCON 25 STOP2 FM MR 7 0 0x00 STOP2 SCU LVDCON 0 LVD_DISABLE SETUP WAKE UP SOURCE SCU CSCR Enable All Clock Wait for stabilizing SCU SCCR LSI SCU CSCR 0x20 only LSI enable SCB SCR 2 1 WFI ENTER POWER DOWN Wait for WAKE UP signal WAKE UP DEFAULT CLOCK LSI RECOVER CLOCK SOURCE SCU SMR 9 Disable Enable LSI CLK STOP SCB SCR 2 1 WFI ENTER POWER DOWN Wait for WAKE UP signal LSI CLK RUNN...

Page 39: ... PIN DESCRIPTION 1 4 Table 1 3 SCU pins PIN NAME TYPE DESCRIPTION nRESET I External Reset Input XIN XOUT OSC External Crystal Oscillator SXIN SXOUT OSC External sub Crystal Oscillator STBO O Stand by Output Signal CLKO O Clock Output Monitoring Signal ...

Page 40: ... clock enable register 1 0000_000F PCER2 0x0034 RW Peripheral clock enable register 2 0000_0101 CSCR 0x0040 RW Clock Source Control register 0000_0020 SCCR 0x0044 RW System Clock Control register 0000_0000 CMR 0x0048 RW Clock Monitoring register 0000_0090 NMIR 0x004C RW NMI control register 0000_0000 COR 0x0050 RW Clock Output Control register 0000_000F VDCCON 0x0064 WO VDC Control register 040F_0...

Page 41: ...ode 1 VDC isn t automatically off entering power down mode 5 4 PREVMODE Previous operating mode before current reset event 00 Previous operating mode was RUN mode 01 Previous operating mode was SLEEP mode 10 Previous operating mode was Power Down mode 11 Previous operating mode was INIT mode SRCR System Reset Control Register 1 5 2 It is possible to check if chip is in power down mode To use STBO ...

Page 42: ...le wakeup source of GPIOD port pin change event 0 Not used for wakeup source 1 Enable the wakeup event generation 10 GPIOCWUE Enable wakeup source of GPIOC port pin change event 0 Not used for wakeup source 1 Enable the wakeup event generation 9 GPIOBWUE Enable wakeup source of GPIOB port pin change event 0 Not used for wakeup source 1 Enable the wakeup event generation 8 GPIOAWUE Enable wakeup so...

Page 43: ...U Status of wakeup source of GPIOD port pin change event 0 No wakeup event 1 Wakeup event was generated 10 GPIOCWU Status of wakeup source of GPIOC port pin change event 0 No wakeup event 1 Wakeup event was generated 9 GPIOBWU Status of wakeup source of GPIOB port pin change event 0 No wakeup event 1 Wakeup event was generated 8 GPIOAWU Status of wakeup source of GPIOA port pin change event 0 No w...

Page 44: ...asked 1 Reset from this event is enabled 6 PINRST External pin reset enable bit 0 Reset from this event is masked 1 Reset from this event is enabled 5 CPURST CPU request reset enable bit 0 Reset from this event is masked 1 Reset from this event is enabled 4 SWRST Software reset enable bit 0 Reset from this event is masked 1 Reset from this event is enabled 3 WDTRST Watchdog Timer reset enable bit ...

Page 45: ...s bit 0 Read Reset from this event was not exist Write no effect 1 Read Reset from this event was occurred Write Clear the status 5 CPURST CPU request reset status bit 0 Read Reset from this event was not exist Write no effect 1 Read Reset from this event was occurred Write Clear the status 4 SWRST Software reset status bit 0 Read Reset from this event was not exist Write no effect 1 Read Reset fr...

Page 46: ...0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FRT TIMER3 TIMER2 TIMER1 TIMER0 GPIOD GPIOC GPIOB GPIOA DIV64 PCU WDT FMC SCU 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 1 1 1 1 RW RW RW RW RW RW RW RW RW RW RW RW RW RW 26 FRT FRT reset enable 19 TIMER3 TIMER3 reset enable 18 TIMER2 TIMER2 reset enable 17 TIMER1 TIMER1 reset enable 16 TIMER0 TIMER0 reset enable 11 GPIOD GPIOD reset...

Page 47: ...x4000_0024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADC MPWM UART1 UART0 I2C SPI 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 RW RW RW RW RW RW 20 ADC ADC reset enable 16 MPWM0 MPWM reset enable 9 UART1 UART1 reset enable 8 UART0 UART0 reset enable 4 I2C I 2 C reset enable 0 SPI SPI reset enable ...

Page 48: ...R1 0x4000_0028 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FRT TIMER3 TIMER2 TIMER1 TIMER0 GPIOD GPIOC GPIOB GPIOA DIV64 Reserved Reserved Reserved Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 RW RW RW RW RW RW RW RW RW RW RO RO RO RO 26 FRT FRT function enable 19 TIMER3 TIMER3 function enable 18 TIMER2 TIMER2 function enable 17...

Page 49: ...0 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADC MPWM UART1 UART0 I2C SPI 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 RW RW RW RW RW RW 20 ADC ADC function enable 16 MPWM MPWM function enable 9 UART1 UART1 function enable 8 UART0 UART0 function enable 4 I2C I 2 C function enable 0 SPI SPI function enable ...

Page 50: ...s stopped PCER1 0x4000_0030 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FRT TIMER3 TIMER2 TIMER1 TIMER0 GPIOD GPIOC GPIOB GPIOA DIV64 Reserved Reserved Reserved Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 RW RW RW RW RW RW RW RW RW RW RW RO RO RO RO 26 FRT FRT clock enable 19 TIMER3 TIMER3 clock enable 18 TIMER2 TIMER2 clock en...

Page 51: ...rrespond PCER2 0x4000_0034 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADC MWPM UART1 UART0 I2C SPI 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 RW RW RW RW RW RW 20 ADC ADC clock enable 16 MPWM MPWM clock enable 9 UART1 UART1 clock enable 8 UART0 UART0 clock enable 4 I2C I 2 C clock enable 0 SPI SPI clock enable ...

Page 52: ...ernal oscillator divide by 2 3 2 HSICON High speed internal oscillator control 0X Disable high speed internal oscillator 10 Enable high speed internal oscillator 11 Enable high speed internal oscillator divide by 2 1 0 MOSCCON External crystal main oscillator control 0X Disable external main crystal oscillator 10 Enable external main crystal oscillator 11 Enable external main crystal oscillator di...

Page 53: ...scillator fail interrupt is pending Write Clear pending interrupt 8 SOSCSTS External sub oscillator status 0 Not oscillate 1 External sub oscillator is working normally 7 MCLKMNT MCLK monitoring enable 0 MCLK monitoring disabled 1 MCLK monitoring enabled 6 MCLKIE MCLK fail interrupt enable 0 MCLK fail interrupt disabled 1 MCLK fail interrupt enabled 5 MCLKFAIL MCLK fail interrupt 0 MCLK fail inter...

Page 54: ...12 PROTSTS Protection condition status bit This bit can t invoke NMI interrupt without enable bit 0 Not occurred 1 Event occurred 11 OVPSTS Over Voltage Protection condition status bit This bit can t invoke NMI interrupt without enable bit 0 Not occurred 1 Event occurred 10 WDTINTSTS WDT Interrupt condition status bit This bit can t invoke NMI interrupt without enable bit 0 Not occurred 1 Event oc...

Page 55: ...ider To use CLKO output function it should be set as CLKO that has output mode in Pin Mux Clock Output Register is 8 bit register COR 0x4000_0050 7 6 5 4 3 2 1 0 CLKOEN CLKODIV 000 0 1111 RO RW RW 4 CLKOEN Clock output enable 0 CLKO is disabled and stay L output 1 CLKO Is enabled 3 0 CLKODIV Clock output divider value CLKO MCLK CLKODIV 0 CLKO 𝑀𝐶𝐿𝐾 2 CLKODIV 1 𝐶𝐿𝐾𝑂𝐷𝐼𝑉 0 ...

Page 56: ...ME VDCMODE value write enable Write only with VDCMODE value 0 VDCMODE field is not updated by writing 1 VDCMODE filed can be updated by writing 25 STOPSEL STOP MODE Select bit 0 VDC STOP MODE 1 1 VDC STOP MODE 2 8 VDCDE VDCWDLY value write enable Write only with VDCWDLY value 0 VDCWDLY Write disable 1 VDCWDLY Write Enable 3 0 VDCWDLY VDC warm up delay count value When SCU is waked up from power do...

Page 57: ...ite enable Write only 0 LVDSEL field is not updated by writing 1 LVDSEL filed can be updated by writing 9 8 LVDSEL LVD detect level select 00 LVD detect level is 1 73V 01 LVD detect level is 2 65V 10 LVD detect level is 3 70V 11 LVD detect level is 4 35V 1 Not Used 1 LVDLVL LVD Status 0 VDDEXT level is over than LVD level 1 VDDEXT level is under than LVD level 0 LVDEN LVD Function enable 0 LVD is ...

Page 58: ... 0 0 RW RW 31 BISCON Build in self calibration function enable 0 BISC function disabled IOSC supplies factory calibrated frequency 1 BISC function enabled IOSC supplies self calibrated frequency 30 REFSEL Reference clock select for self calibration 0 Main oscillator clock source is reference clock 1 Sub oscillator clock source is reference clock CAUTION you must not set the reserved bit field Note...

Page 59: ...24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTOSC_COMP XTAL_COMP 0 0 RW RW 31 16 INTOSC_COMP 31 16 INTOSC compare value 15 0 XTAL_COMP 15 0 XTAL Compare value Calibration supports below configurations on the table Table 1 6 BISC count value XTAL FREQ TARGET FREQ UPDATE PERIOOD XTAL_COMP INTOSC_COMP MHz MHz Nano Sec Count Value Count Value 10 40 10 000 99 399 8 40 1 000 000 79...

Page 60: ...LKEN 0 0 0 0 WO RW WO RW 15 FILSKIPWEN Write enable of bit field FILSKIPEN 0 Write access of FILSKIPEN field is masked 1 Write access of FILSKIPEN field is accepted 8 FILSKIPEN Control External Main Oscillator Filter Skip bit 0 External Main Oscillator Filter Skip Disable 1 External Main Oscillator Filter Skip Enable 7 INVCLKWEN Write enable of bit field FILSKIPEN 0 Write access of INVCLKEN field ...

Page 61: ...de Status Register 1 5 23 External Mode Status Register shows external mode pin status while booting This register is 8 bit register EMODR 0x4000_0084 7 6 5 4 3 2 1 0 Reserved Reserved BOOT 0x0 RO RO 0 BOOT BOOT pin level 0 BOOT PC11 pin is low 1 BOOT PC11 pin is high ...

Page 62: ... SYSTICK external clock source This register is 32 bit register MCCR1 0x4000_0090 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Reserved Reserved STCSEL STCDIV 000 0x00 RW RW 10 8 STCSEL SYSTICK Clock source select bit 000 LSI 100 MCLK 101 HSI 110 MOSC 111 Reserved 7 0 STCDIV SYSTICK Clock N divider 0x00 disabled 0xN selected clock N To change the v...

Page 63: ...sed MPWM it must set this register This register is 32 bit register MCCR2 0x4000_0094 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Reserved PWMCSEL PWMDIV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000 0x00 RW RW 10 8 PWMCSEL PWM Clock source select bit 000 LSI 100 MCLK 101 HSI 110 MOSC 111 Reserved 7 0 PWMDIV PWM Clock N divider 0x00 disabled 0xN s...

Page 64: ... 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TIMERCSEL TIMERDIV WDTCSEL WDTDIV 0 0 0 0 0 000 0x01 0 0 0 0 0 000 0x01 RW RW RW RW 26 24 TIMERCSEL Timer Clock source select bit 000 LSI 100 MCLK 101 HSI 110 MOSC 111 SOSC 23 16 TIMERDIV Timer Clock N divider 0x00 disabled 0xN selected clock N To change the value set 0x0 first without changing TIMERCSEL 10 8 WD...

Page 65: ... 11 10 9 8 7 6 5 4 3 2 1 0 PBDCSEL PBDDIV PADCSEL PADDIV 0 0 0 0 0 000 0x01 0 0 0 0 0 000 0x01 RW RW RW RW 26 24 PBDCSEL Debounce Clock for Port B source select bit 000 LSI 100 MCLK 101 HSI 110 MOSC 111 SOSC 23 16 PBDDIV PORT B Debounce Clock N divider 0x00 disabled 0xN selected clock N To change the value set 0x0 first without changing PBDCSEL 10 8 PADCSEL Debounce Clock for Port A source select ...

Page 66: ...11 10 9 8 7 6 5 4 3 2 1 0 PDDCSEL PDDDIV PCDCSEL PCDDIV 0 0 0 0 0 000 0x01 0 0 0 0 0 000 0x01 RW RW RW RW 26 24 PDDCSEL Debounce Clock for PORT D source select bit 000 LSI 100 MCLK 101 HSI 110 MOSC 111 SOSC 23 16 PDDDIV PORT D Debounce Clock N divider 0x00 disabled 0xN selected clock N To change the value set 0x0 first without changing PDDCSEL 10 8 PCDCSEL Debounce Clock for PORT C source select b...

Page 67: ...0_00A8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCCSEL ADCCDIV UARTCSEL UARTCDIV 0 0 0 0 0 000 0x01 000 0x01 RW RW RW RW 26 24 ADCCSEL ADC clock source select bit 000 LSI 100 MCLK 101 HSI 110 MOSC 111 Reserved 23 16 ADCCDIV ADC Clock N divider 0x00 disabled 0xN selected clock N To change the value set 0x0 first without changing ADCCSEL 10 8 UARTCSEL UA...

Page 68: ...l be changed until the frequency of INTOSC cross the target frequency level 8 steps up trim and 8 steps down trim are available with 0 7 difference in each step Update period is decided by reference clock counter value When BISC function enabled factory calibration value is replaced by self calibration value Minimum 8 times of update period time is required before changing system clock to INTOSC c...

Page 69: ...69 246 ABOV Semiconductor Port Control Unit PCU PORT CONTROL UNIT PCU CHAPTER 2 ...

Page 70: ...ernal I Os as below Set pin function mux Set external signal directions of each pins Set interrupt trigger mode for each pins Set internal pull up register control and open drain control PORT CONTROL FUNCTION MUX INTERRUPT CONTROL NVIC APB BUS Function I Os PA PB PC PD PORTs Figure 2 1 Block diagram ...

Page 71: ...ebounce count Pull up Enable Analog input AN0 AN11 XIN XOUT SXIN SXOUT VDDIO VDDIO PIN Figure 2 2 I O Port Block Diagram ADC and External Oscillator pins Open drain Enable Input mode 00 01 10 11 Port MUX GPIO output Function 1 output Function 2 output Function 3 output VDDIO 0 1 Analog disable Function input Debounce enable Debounce Logic Debounce count Pull up Enable VDDIO VDDIO PIN Figure 2 3 I ...

Page 72: ...0 1 PA1 T3IO AIN1 2 PA2 SS WDTO AIN2 3 PA3 SCK STBO AIN3 4 PA4 AIN4 5 PA5 AIN5 6 PA6 T0IO AIN6 7 PA7 T1IO AIN7 8 PA8 T2IO T0IO AIN8 9 PA9 T3IO T1IO AIN9 10 PA10 AIN10 11 PA11 AIN11 12 PA12 T0IO 13 PA13 T1IO 14 PA14 T2IO 15 PA15 T3IO PB 0 PB0 MPWMUH SS 1 PB1 MPWMUL SCK 2 PB2 MPWMVH MOSI 3 PB3 MPWMVL MISO 4 PB4 MPWMWH 5 PB5 MWMWL 6 PB6 PRTIN 7 PB7 OVIN 8 9 10 11 12 13 14 15 mark indicates default pi...

Page 73: ... 2 PC2 3 PC3 4 PC4 T0IO 5 PC5 RXD1 T1IO 6 PC6 TXD1 T2IO 7 PC7 SCL T3IO 8 PC8 SDA VMRG 9 PC9 CLKO 10 PC10 nRESET 11 PC11 BOOT T0IO 12 PC12 T3IO XIN 13 PC13 T2IO XOUT 14 PC14 RXD0 15 PC15 TXD0 PD 0 PD0 SS 1 PD1 SCK 2 PD2 MOSI SCL SXOUT 3 PD3 MISO SDA SXIN 4 5 6 7 8 9 10 11 12 13 14 15 mark indicates default pin setting 2 mark indicates secondary port ...

Page 74: ...RESS PCA 0x4000_1000 PCB 0x4000_1100 PCC 0x4000_1200 PCD 0x4000_1300 Table 2 4 PCU Register map NAME OFFSET TYPE DESCRIPTION PCn MR 0x 00 RW Port n pin mux select register PCn CR 0x 04 RW Port n pin control register PCn PCR 0x 08 RW Port n internal pull up control register PCn DER 0x 0C RW Port n debounce control register PCn IER 0x 10 RW Port n interrupt enable register PCn ISR 0x 14 RW Port n in...

Page 75: ... 11 10 9 8 7 6 5 4 3 2 1 0 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW PORT SELECTION BIT 00 01 10 11 PA0 PA0 T2IO AIN0 PA1 PA1 T3IO AIN1 PA2 PA2 SS WDTO AIN2 PA3 PA3 SCK STBO AIN3 PA4 PA4 AIN4 PA5 PA5 AIN5 PA6 PA6 T0IO AIN6 PA7 PA7 T1IO AIN7 PA8 PA8 T2IO T0IO AIN8 PA9 PA9 T3IO...

Page 76: ... 0x4000_1100 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW PORT SELECTION BIT 00 01 10 11 PB0 PB0 MPWMUH SS PB1 PB1 MPWMUL SCK PB2 PB2 MPWMVH MOSI PB3 PB3 MPWMVL MISO PB4 PB4 MPWMWH PB5 PB5 MPWM...

Page 77: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 00 00 00 00 01 01 00 00 00 00 00 00 00 00 01 01 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW PORT SELECTION BIT 00 01 10 11 PC0 PC0 SWCLK RXD1 PC1 PC1 SWDIO TXD1 PC2 PC2 PC3 PC3 PC4 PC4 T0IO PC5 PC5 RXD1 T1IO PC6 PC6 TXD1 T2IO PC7 PC7 SCL T3IO PC8 PC8 SDA VMRG PC9 PC9 CLKO PC10 PC10 nRESE...

Page 78: ...uarantee its functionality PCD MR 0x4000_1300 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW PORT SELECTION BIT 00 01 10 11 PD0 PD0 SS PD1 PD1 SCK PD2 PD2 MOSI SCL SXOUT PD3 PD3 MISO SDA SXIN ...

Page 79: ...ach port pin Each pin can be configured as input pin output pin or open drain pin PCC CR 0x4000_1204 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 11 11 11 11 10 10 11 11 11 11 11 11 11 11 10 10 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Pn Port control 00 Push pull output 01 Open drain output 10 Inp...

Page 80: ...DE15 PDE14 PDE13 PDE12 PDE11 PDE10 PDE9 PDE8 PDE7 PDE6 PDE5 PDE4 PDE3 PDE2 PDE1 PDE0 0000 RW PDEn Pin debounce enable 0 Disable debounce filter 1 Enable debounce filter PCn IER PORT n Interrupt Enable Register 2 3 10 The entire pin can be an external interrupt source Both of edge trigger interrupt and level trigger interrupt are supported The interrupt mode can be configured by setting PCn IER reg...

Page 81: ...edge interrupt event is present 10 High level interrupt or rising edge interrupt event is present 11 Both of rising and falling edge interrupt event is present in edge trigger interrupt mode Not available in level trigger interrupt mode PCn ICR PORT n Interrupt Control Register 2 3 12 Interrupt mode control register PCA ICR 0x4000_1018 PCB ICR 0x4000_1118 PCC ICR 0x4000_1218 PCD ICR 0x4000_1318 31...

Page 82: ...4000_1FF0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PORTEN 0 0 0 0 0 0 0 0 WO 7 0 PORTEN Writing the sequence of 0x15 and 0x51 in this register enables writing to PCU registers and writing other values protects all PCU registers from writing Note how to use PORTEN PORTEN 0x15 PORTEN 0x51 enable PORTEN set PCn MR PCn CR PCn PCR and etc PORTEN 0 disable PORTEN ...

Page 83: ...NC 3 IN Control logic Pin Control register VDDIO PAD R W R W R W R W VDDIO OUTPUT CONTROL LOGIC INPUT CONTROL LOGIC AIN5V 200 Ohm 200 Ohm Figure 2 4 Functional Bloack diagram When the input functions of I O port is used by Pin Control Register the output function of I O port is disabled The Port Function different according to the Pin Mux Register The Input Data Register capture the data present o...

Page 84: ... each port group used by MCCR4 5 Register 2 bit UP DOWN Counter External Input PORT in UP 1 DOWN 0 FF CNT 1 0 CLK Debounce Clock Internal Input CNT 1 0 01à 1 CNT 1 0 10à 0 Counter operation If PORT In 1 CNT 1 0 01 CNT 1 0 UP Else if PORT In 0 CNT 1 0 10 CNT 1 0 DOWN Figure 2 5 Debounce Logic External Input PORT in CNT 1 0 01b 00b 11b 10b Internal Input Debounced in Debounce CLK 1 1 1 1 0 1 0 0 0 1...

Page 85: ...85 246 ABOV Semiconductor General Purpose I O GPIO GENERAL PURPOSE I O GPIO CHAPTER 3 ...

Page 86: ... of pins except dedicated function pins can be used general I O ports General input output ports are controlled by GPIO block Output signal level H L select Read Input signal level Pn BSR Pn BCR Pn ODR Pn IDR DIN 31 0 PSEL DOUT 31 0 PCU PINs Figure 3 1 Block diagram ...

Page 87: ...87 246 ABOV Semiconductor General Purpose I O GPIO Pin description 3 2 Table 3 1 External signal PIN NAME TYPE DESCRIPTION PA IO PA0 PA15 PB IO PB0 PB7 PC IO PC0 PC15 PD IO PD0 PD3 ...

Page 88: ...port NAME BASE ADDRESS PA PORT 0x4000_2000 PB PORT 0x4000_2100 PC PORT 0x4000_2200 PD PORT 0x4000_2300 Table 3 3 GPIO Register map NAME OFFSET TYPE DESCRIPTION RESET VALUE Pn ODR 0x 00 RW Port n Output data register 0x00000000 Pn IDR 0x 04 RO Port n Input data register 0x00000000 Pn BSR 0x 08 WO Port n Pin set register 0x00000000 Pn BCR 0x 0C WO Port n Pin clear register 0x00000000 ...

Page 89: ...7 6 5 4 3 2 1 0 ODR 0000 RW ODR Pin output level 0 Output low level 1 Output high level Pn IDR PORT n Input Data Register 3 3 2 Each pin level status can be read in the Pn IDR register Even if the pin is alternative mode except analog mode the pin level can be detected in the Pn IDR register PA IDR 0x4000_2004 PB IDR 0x4000_2104 PC IDR 0x4000_2204 PD IDR 0x4000_2304 15 14 13 12 11 10 9 8 7 6 5 4 3...

Page 90: ... 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BSR 0000 WO BSR Pin current level 0 Not effect 1 Set correspondent bit in Pn ODR register Pn BCR PORT n Bit Clear Register 3 3 4 Pn BCR is a register for control each bit of Pn ODR register Writing a 1 into the specific bit will set a corresponding bit of Pn ODR to 0 Writing 0 in this register has no effect PA BCR 0x4000_200C PB BCR 0x4000_210C PC BCR 0x4000_220C P...

Page 91: ...ONTROL UNIT GPIO BLOCK Figure 3 2 Functional Block diagram When configured as output the value written to the GPIO Output Data Register is output on the I O Pin When set the Bit Set Register GPIO Output Data Register set the high When set the Bit Clr Register GPIO Output Data Register set the Low The Input Data Register capture the data present on the I O pin or Debounced input data at every GPIO ...

Page 92: ...92 246 92 246 AC30M1x64 1x32 ABOV Semiconductor FLASH MEMORY CONTROLLER CHAPTER 4 ...

Page 93: ...der 20MHz 1 wait 2 wait and pre fetch read acceleration access support Use internal 40MHz OSC clock to make timing control for Erase Program Start address FLASH MEMORY 64KB 0x0000_0000 0x0000_1000 0x0000_2000 0x0000_3000 0x0000_4000 0x0000_5000 0x0000_6000 0x0000_7000 0x0000_8000 0x0000_9000 0x0000_A000 0x0000_B000 0x0000_C000 0x0000_D000 0x0000_E000 0x0000_F000 WPROT WP 0 WP 1 WP 2 WP 3 WP 4 WP 5...

Page 94: ...ory Control register 0x05000000 FM AR 0x000C RW Flash Memory Address register 0x00000000 FM DR 0x0010 RW Flash Memory Data register 0x00000000 FM TMR 0x0014 RW Flash Memory Timer register 0x00018FFF FM TICK 0x001C R Flash Memory Tick Timer 0x00000000 FM CRC 0x0020 R Flash CRC16 check value 0x00000000 FM CFG 0x0030 RW Flash Memory Configuration value 0x00008200 FM HWID 0x0040 R Second HW ID for AC3...

Page 95: ...ster enable 0 means can set TEST reg 22 AMBAEN 0 AMBA mode disabled status 1 AMBA mode enable can change wait state and etc 21 PROTEN 0 Flash protection register disable 0 means cannot access protection register 1 Flash protection register enable 1 means can access protection register 17 TRMEN 0 TRIM mode disabled status 1 Trim mode entry status read only 16 TRM 0 TRIM mode disabled 1 Trim mode st...

Page 96: ... 1 OTP area 1 access enable user can access in a certain condition OTP1 is used for read protection 28 OTP0 0 1 OTP area 0 access enable user can not erase program this area 20 TMREN 0 Flash Tick timer enable 1 Flash tick timer enable Tick timer runs by system clock while PGM or ERS undergoing 17 16 TEST 1 0 00 Normal operation 01 read Row voltage mode 01 write ODD Row program 10 Even Row program ...

Page 97: ...97 246 ABOV Semiconductor Flash Memory Controller 1 Write enable 3 PBLD 0 1 Page buffer load WE should be set 2 PGM 0 1 Program mode enable 1 ERS 0 1 Erase mode enable 0 PBR 0 1 Page buffer reset ...

Page 98: ...y program data register FM DR 0x4000_0110 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FDATA 0x0000_0000 RW 31 0 FDATA Flash PGM data 32 bit FM TMR Flash Memory Timer Register 4 2 5 Internal flash memory Timer value register 18 bit Erase Program timer runs up to TMR 17 0 FM TMR 0x4000_0114 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 ...

Page 99: ... 0x3FFFF from written TICK value while TMR runs by PCLK clock while Flash PGM or ERS counts up only when IDLE bit of FMMR register is low FM CRC Flash CRC check register 4 2 7 FMCRC is the CRC value resulted from read accesses on internal flash memory FM CRC 0x4000_012C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CRC16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x000...

Page 100: ...ESTCLK 0 TEST Clock selection test purpose only Set 1 to use system bus clock instead of internal 40MHz OSC This bits only be written in AMBA mode and MSB 16 bit bit 31 16 must be 0x7858 9 8 WAIT This bits only be written in AMBA mode and MSB 16 bit bit 31 16 must be 0x7858 00 WAIT is 00 flash access in 1 cycle 0 wait 01 WAIT is 01 flash access in 2 cycles 1 wait 10 WAIT is 10 flash access in 3 cy...

Page 101: ...gister is 32 bit read only register FM HWID 0x4000_0140 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FHWID 0x3014_6400 R 31 0 FHWID Flash HWID register It returns size option values 0x30146400 64KB flash product option 0x30143200 32KB flash product option 0x30FF0000 wrong size option code 64KB flash enable ...

Page 102: ...le when AMBA mode is enabled FM MR 0x81 FM MR 0x28 AMBA mode enter change BOOTCR 4 SREMAP value FM MR 0 AMBA mode exit FM WPROT Flash Memory Write Protection Register 4 2 11 Internal flash memory write protection register This registers will be update from OTP area of Flash while boot sequence so user cannot write or clear any bit directly FM WPROT 0x4000_0178 31 30 29 28 27 26 25 24 23 22 21 20 1...

Page 103: ... SRAM or debugger 0xA5A5A5A5 will be return as read data LOCK2 Read protection level 2 Code protection mode enable debug cannot be connected Write any value except 0x39 include 0xFF to activate LOCK2 only can be written in Unlock state or LOCK1 When flash was read from SRAM 0xA5A5A5A5 will be return as read data Flash Erase and Program examples 4 2 13 The basic step of Flash memory program consist...

Page 104: ... PMODE bit of FM CR J Clear Flash mode write 0x00 into FM MR K Insert at least 2 NOPs and return to normal operation 3 Program example include page buffer load A Flash mode enable to write FM CR register write 0x5A and then write 0xA5 into FM MR B Set FM TMR register to be 2 5ms operation based on 40MHz Int OSC clock C Set target Page address in FM AR D Set PMODE bit first E Set PBR bit of FM CR a...

Page 105: ...105 246 ABOV Semiconductor Internal SRAM INTERNAL SRAM CHAPTER 5 ...

Page 106: ... is 4KB The SRAM base address is 0x2000_0000 The SRAM memory area is usually used for data memory and stack memory Sometimes the code is dumped into the SRAM memory for fast operation or flash erase pgm operation This device does not support memory remap strategy So jump and return is required to perform the code in SRAM memory area ...

Page 107: ...107 246 ABOV Semiconductor Watch Dog Timer WATCH DOG TIMER WDT CHAPTER 6 ...

Page 108: ... down counter WDT CNT Select reset or periodic interrupt Count clock selection Dedicated pre scaler Watchdog underflow output signal APB interface WDT_RESETn WDTRE WDT CON 6 WDT LOGIC WUF WDT CON 8 WDTIE WDT CON 7 WDT Internal counter WDT prescale WDT REGISTER WPRS WDT CON 2 0 WDT LR WDT CON WDT CNT WDT_INT underflow SEL MUX PCLK EXTCLK SCU MCCR3 Figure 6 1 WDT Block diagram ...

Page 109: ...d write into WDTLR register with target value of WDTCNT It needs at least 5 WDT clocks to update WDTLR to WDTCNT WDT ext clock source is controlled by WDTCSEL and WDTDIV in MCCR3 WDT LR 0x4000_0200 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDTLR 0x0000_0000 RW 31 0 WDTLR Watchdog timer load value register Keeping WEN bit as 1 write WDTLR register will up...

Page 110: ...ng when debug mode 1 Watchdog counter stopped when debug mode 8 WUF Watchdog timer underflow flag 0 No underflow 1 Underflow is pending 7 WDTIE Watchdog timer counter underflow interrupt enable 0 Disable interrupt 1 Enable interrupt 6 WDTRE Watchdog timer counter underflow interrupt enable 0 Disable reset 1 Enable reset 4 WDTEN Watchdog Counter enable 0 Watch dog counter disabled 1 Watch dog count...

Page 111: ... WDT CON It takes up to 5 cycles from Load value to the CNT value The WDT interrupt signal and CNT value data might be delayed maximum by 2 system bus clocks in synchronous logic Prescale Table 6 3 2 The WDT includes a 32 bit down counter with programmable pre scaler to define different time out intervals The clock sources of watchdog timer can be peripheral clock PCLK or one of 5external clock so...

Page 112: ...64 WDTCLKIN 128 WDTCLKIN 256 LSI 40kHz 10kHz 5kHz 2 5kHz 1 25kHz 0 625kHz 0 3125kHz 0 15625kHz MCLK Bus clock MCLK 4 MCLK 8 MCLK 16 MCLK 32 MCLK 32 MCLK 128 MCLK 256 HSI 40MHz 10MHz 5MHz 2 5MHz 1 25MHz 0 625MHz 0 3125MHz 0 15625MHz MOSC XTAL frequency 4MHz 16MHz XTAL 4 XTAL 8 XTAL 16 XTAL 32 XTAL 64 XTAL 128 XTAL 256 SOSC 32 768kHz 8 192kHz 4 096kHz 2 048kHz 1 024kHz 0 512kHz 0 256kHz 0 128kHz ...

Page 113: ...113 246 ABOV Semiconductor 16 bit Timer 16 BIT TIMER CHAPTER 7 ...

Page 114: ...rt periodic timer PWM pulse one shot timer and capture mode They can be synchronized together One more optional free run timer is provided The main purpose of this timer is a periodical tick timer or a wake up source 16 bit up counter Periodic timer mode One shot timer mode PWM pulse mode Capture mode 10 bit prescaler Synchronous start and clear function Figure 7 1 shows the block diagram of a uni...

Page 115: ...115 246 ABOV Semiconductor 16 bit Timer Pin description 7 2 Table 7 1 External pin PIN NAME TYPE DESCRIPTION TnIO I O External clock capture input and PWM one shot output ...

Page 116: ...imer Register Map NAME OFFSET TYPE DESCRIPTION RESET VALUE Tn CR1 0x 00 RW Timer control register 1 0x00000000 Tn CR2 0x 04 RW Timer control register 2 0x00000000 Tn PRS 0x 08 RW Timer prescaler register 0x00000000 Tn GRA 0x 0C RW Timer general data register A 0x00000000 Tn GRB 0x 10 RW Timer general data register B 0x00000000 Tn CNT 0x 14 RW Timer counter register 0x00000000 Tn SR 0x 18 RW Timer ...

Page 117: ...ounter with other synchronized timers 0 Single counter mode 1 Synchronized counter clear mode 13 UAO Select GRA GRB update mode 0 Writing GRA or GRB takes effect after current period 1 Writing GRA or GRB takes effect in current period 12 OUTPOL Timer output polarity 0 Normal output 1 Negated output 8 ADCTRGEN ADC Trigger enable control 0 Disable adc trigger 1 Enable adc trigger at same time of GRA...

Page 118: ...t register This bit will be cleared after next timer clock 0 TEN Timer enable bit 0 Stop timer counting 1 Start timer counting Note It is recommended to start timer with TCLR bit setting to be 1 Tn PRS Timer n Prescaler Register 7 3 3 Timer Prescaler Register is 16 bit register in order to prescale the counter input clock T0 PRS 0x4000_3008 T1 PRS 0x4000_3028 T2 PRS 0x4000_3048 T3 PRS 0x4000_3068 ...

Page 119: ...ing edge of TnIO port will capture the count value when falling edge clear mode Tn GRB Timer n General Register B 7 3 5 Timer General Register B is 16 bit register T0 GRB 0x4000_3010 T1 GRB 0x4000_3030 T2 GRB 0x4000_3050 T3 GRB 0x4000_3070 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GRB 0x0000 RW 15 0 GRB General Register B Period Register Periodic mode PWM One shot mode In periodic mode or PWM mode thi...

Page 120: ...first count 0xFF Prescaler will not be initialized and maintain current conditions even writing timer count value on Tn CNT 15 0 First count period is not accurate depends on its status when writing operation 15 0 CNT Timer count value register R Read current timer count value W Set count value Tn SR Timer n Status Register 7 3 7 Timer Status Register is 8 bit register This register indicates the ...

Page 121: ...in correspondent bit in the Tn IER register T0 IER 0x4000_301C T1 IER 0x4000_303C T2 IER 0x4000_305C T3 IER 0x4000_307C 7 6 5 4 3 2 1 0 MAIE MBIE OVIE 0 0 0 0 0 0 0 0 RW RW RW 2 MAIE GRA Match interrupt enable 0 Not effect 1 Enable match register A interrupt 1 MBIE GRB Match interrupt enable 0 Not effect 1 Enable match register B interrupt 0 OVIE Counter overflow interrupt enable 0 Not effect 1 En...

Page 122: ...ration The period of timer count can be calculated as below equation The period TMCLK Period Tn GRB value Match A interrupt time TMCLK Period Tn GRA value If Tn CR1 UAO bit is 0 Tn CR2 TCLR command will initialize all the registers in timer block and load the GRA and GRB value into Data0 and Data1 buffer When you change the timer setting and restart the timer with new setting it s recommended that...

Page 123: ...RB 0 the timer cannot be started even Tn CR2 TEN is 1 That s because the period is 0 The value in Tn GRA and Tn GRB is loaded into internal compare data buffer 0 and 1 when the loading condition is occurred In this periodic mode with Tn CR1 UAO 0 Tn CR2 TCLR write operation will load the data buffer and the next GRB match event will load the data buffer When Tn CR1 UAO is 1 the internal compare da...

Page 124: ...f Tn GRB 0 the timer cannot be started even Tn CR2 TEN is 1 Because the period is 0 The value in Tn GRA and Tn GRB is loaded into internal compare data buffer 0 and 1 when the loading condition is occurred In this periodic mode with Tn CR1 UAO 0 Tn CR2 TCLR write operation will load the data buffer and the next GRB match event will load the data buffer When Tn CR1 UAO is 1 the internal compare dat...

Page 125: ...ffer 0 and 1 when the loading condition is occurred In this periodic mode with Tn CR1 UAO 0 Tn CR2 TCLR write operation will load the data buffer and the next GRB match event will load the data buffer When Tn CR1 UAO is 1 the internal compare data buffer is updated whenever the Tn GRA or Tn GRB data is updated TnIO output signal generates pwm pulse Tn GRB value defines the output pulse period and ...

Page 126: ...RA T0 CNT T0 GRB T1 CNT T1 GRB For timing synchronization every GRB register should have same values T0 GRB T0 GRA T1 CR2 TEN 1 T1 CNT Timer0 was cleared by start event of Timer1 Timer0 restarts Timer0 starts Timer1 starts T0 T1 CNT T0IO output T1IO output T0 GRB T1 GRB T0 GRA T1 GRA T0 CNT 0 T1 CNT 0 T1 CNT T1 GRA T0 CNT T0 GRA T0 CNT T0 GRB The fastest clear condition will clear all the synchron...

Page 127: ...capture the counter valued in each capture conditions Figure 7 8 Capture mode timing diagram 5 PCLK clock cycle is required internally So actual capture point is after 5 PCLK clock cycles from rising or falling edge of TnIO input signal Internal counter can be cleared in various mode Tn CR1 CLRMD field controls the counter clear mode Rising edge clear mode falling edge clear mode both edge clear m...

Page 128: ...128 246 128 246 ABOV Semiconductor AC30M1x64 1x32 Figure 7 9 ADC trigger function timing diagram ...

Page 129: ...129 246 ABOV Semiconductor FRT FREE RUN TIMER FRT CHAPTER 8 ...

Page 130: ...ock is a 32 bit Free Run Timer It can be used in Power down Mode 32 bit up counter with SOSC MOSC LSI Matched Interrupt APB LSI CLK MOSC CLK SOSC CLK FRT 00 01 10 32 DIVIDER FRT MR 5 4 32 Bit FRT CNT FRT PER Match Compare Overflow Compare FRT IRQ Figure 8 1 FRT block diagram ...

Page 131: ...f channel NAME BASE ADDRESS FRT 0x4000_0600 Table 8 2 FRT register map NAME OFFSET TYPE DESCRIPTION RESET VALUE FRT MR 0x0000 RW FRT mode register 0x00000000 FRT CR 0x0004 RW FRT control register 0x00000000 FRT PER 0x0008 RW FRT period match register 0x00000000 FRT CNT 0x000C RO FRT counter register 0x00000000 FRT SR 0x0010 RW FRT status register 0x00000000 ...

Page 132: ... Whenever the counter matches FRT PER the counter will be set zero and waiting for MF to be cleared 1 Counter Match Clear function is disabled The counter will keep countering without set zero 1 OVIE Over Flow Interrupt Enable bit 0 Not effect 1 Interrupt enabled 0 MIE Match Interrupt Enable bit 0 Not effect 1 Interrupt enabled FRT CR FRT Control Register 8 2 2 FRT Control Register is 8 bit regist...

Page 133: ... 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT 0x0000_0000 RO 32 0 CNT FRT Counter FRT SR FRT Status Register 8 2 5 FRT Status Register is 8 bit register FRT SR 0x4000_0610 7 6 5 4 3 2 1 0 RACK OVF MF 0 0 0 0 0 0 0 0 WC1 WC1 WC1 2 RACK Read Counter Acknowledge bit 0 Not ready to read CNT value 1 Ready to read CNT value 1 OVF OverFlow Interrupt flag bit 0 Overflow interrupt did not...

Page 134: ...134 246 134 246 ABOV Semiconductor AC30M1x64 1x32 FUNCTION DESCRIPTION 8 3 ...

Page 135: ...135 246 UART ABOV Semiconductor UNIVERSAL ASYNCHRONOUS CHAPTER 9 RECEIVER TRANSMITTER UART ...

Page 136: ...nternally divided by 16 of the prescaled clock and 8 bit precision clock tuning function Programmable interrupt generation function will help to control the communication via UART channel Compatible with 16450 Standard asynchronous control bit start stop and parity configurable Programmable 16 bit fractional baud generator Programmable serial communication 5 6 7 or 8 bit data transfer Even odd or ...

Page 137: ...ER TRANSMITTER HOLDING REGISTER INTERRUPT ENABLE REGISTER BAUD GENERATOR TRNASMITTER TIMING CONTROL TRANSMITTER BUFFER RECEIVER TIMING CONTROL RECEIVER BUFFER DIVISOR LATCH LSB DIVISOR LATCH MSB BFR Fraction RECEIVER SHIFT REGISTER TRANSMITTER SHIFTER REGISTER SELECT INTERRUPT CONTROL LOGIC SELECT INTERRUPT ADDR 4 2 nRESET DATA 7 0 PSEL PWRITE PENABLE PCLK TxD RxD ...

Page 138: ...V Semiconductor Pin description 9 2 Table 9 1 External signal PIN NAME TYPE DESCRIPTION TXD0 O UART Channel 0 transmit output RXD0 I UART Channel 0 receive input TXD1 O UART Channel 1 transmit output RXD1 I UART Channel 1 receive input ...

Page 139: ...CR 0x0C RW Line control register 0x00 Un DCR 0x10 RW Data Control Register Un LSR 0x14 R Line status register 0x00 0x18 reserved Un SCR 0x1C RW Scratch pad register 0x00 Un BDR 0x20 RW Baud rate Divisor Latch Register 0x0000 Un BFR 0x24 RW Baud rate Fractional Counter Value 0x00 Un IDTR 0x30 RW Inter frame Delay Time Register 0x00 Un RBR Receive Buffer Register 9 3 1 UART Receive Buffer Register i...

Page 140: ...gister U0 IER 0x4000_8004 U1 IER 0x4000_8104 7 6 5 4 3 2 1 0 TXIEN RXIEN RLSIE THREIE DRIE 0 0 0 0 0 0 0 0 RW RW RW RW RW 5 TXIEN Transmit done interrupt enable 0 Receive line status interrupt is disabled 1 Receive line status interrupt is enabled 4 RXIEN Receiver line status interrupt enable 0 Receive line status interrupt is disabled 1 Receive line status interrupt is enabled 2 RLSIE Receiver li...

Page 141: ... empty flag 16 DR Data receive interrupt flag 4 TXE Interrupt source ID See interrupt source ID table 3 1 IID Interrupt source ID See interrupt source ID table 0 IPEN Interrupt pending bit 0 Interrupt is pending 1 No interrupt is pending The UART supports 3 priority interrupt generation and interrupt source ID register shows one interrupt source which has highest priority among pending interrupts ...

Page 142: ...1 1 0 Receiver Line Status Overrun Parity Framing or Break Error Read LSR register 2 0 1 0 0 Receiver Data Available Receive data is available Read receive register or read IIR register 3 0 0 1 0 Transmitter Holding Register Empty Transmit buffer empty Write transmit hold register or read IIR register 4 1 X X X Transmitter Register Empty Transmit register empty Write transmit hold register or read...

Page 143: ...RITY 4 PARITY Parity mode selection bit and stuck parity select bit 0 Odd parity mode 1 Even parity mode 3 PEN Parity bit transfer enable 0 The parity bit disabled 1 The parity bit enabled 2 STOPBIT The number of stop bit followed by data bits 0 1 stop bit 1 1 5 2 stop bit In case of 5 bit data case 1 5 stop bit is added In case of 6 7 or 8 bit data 2 stop bit is added 1 0 DLEN The data length in ...

Page 144: ...data line of Tx or RX signal will be inverted U0 DCR 0x4000_8010 U1 DCR 0x4000_8110 7 6 5 4 3 2 1 0 LBON RXINV TXINV 0 0 0 0 0 0 0 0 RW RW RW 4 LBON Local loopback test mode enable 0 Normal mode 1 Local loopback mode TxD connected to RxD internally 3 RXINV Rx Data Inversion Selection 0 Normal RxData Input 1 Inverted RxData Input 2 TXINV Tx Data Inversion Selection 0 Normal TxData Output 1 Inverted...

Page 145: ...g error The receive character did not have a valid stop bit 2 PE Parity Error 0 No parity error 1 Parity error The receive character does not have correct parity information 1 OE Overrun error 0 No overrun error 1 Overrun error Additional data arrives while the RHR is full 0 DR Data received 0 No data in receive holding register 1 Data has been received and is saved in the receive holding register...

Page 146: ...properly The programmable baud rate generate is provided to give from 1 to 65535 divider number The 16 bit divider register UnBDR should be written for expected baud rate UARTclock gets from MCCR7 Baud rate calculation formula is below BDR 𝑈𝐴𝑅𝑇𝑐𝑙𝑜𝑐𝑘 16 𝐵𝑎𝑢𝑑𝑅𝑎𝑡𝑒 In case of 40 MHz UARTclock speed the divider value and error rate is described in table Table9 6 Example of baud rate calculation without...

Page 147: ...4800 520 213 0 00 9600 260 106 0 00 19200 130 53 0 00 38400 65 262 0 00 57600 43 103 0 00 115200 21 179 0 01 FCNT Float 256 FCNT value can calculated above equation For example the target baud rate is 4800 bps and UARTclock is 40MHz case the BDR value is 520 8333 The integer number 520 should be the BDR value and the floating number 0 8333 will make the FNCT value as below FCNT 0 8333 256 213 3333...

Page 148: ...ample will be done at 8 16 baud rate for the start bit 1 Multi sampling is enabled for start bit Sampling is done 3 times at 7 16 8 16 and 9 16 baud rate Dominant value of 3 samples will be selected for the start bit 6 DMS Data Bit Multi sampling enable 0 Multi sampling is disable for data bit Single sample will be done at 8 16 baud rate for the data bit 1 Multi sampling is enabled for data bit Sa...

Page 149: ...rates as following timing If the falling edge on the receive line UART judges as the start bit From the start timing UART oversamples 16 times of 1 bit and detect the bit value at the 7th sample of 16 samples Figure 9 3 The Sampling Timing of UART Receiver It is recommended to enable debounce settings in the PCU block to reinforce the immunity of external glitch noise UnRXD Subsample 0 1 2 3 4 5 6...

Page 150: ... data format is below Figure 9 4 Transmit data format example Inter frame delay transmission 9 4 3 The inter frame delay function allows the transmitter to insert an idle state on the TXD line between 2 characters The width of the idle state is defined in WAITVAL field in Un IDTR register When this field is set 0 no time delay is generated Otherwise the transmitter holds a high level on TXD after ...

Page 151: ...151 246 ABOV Semiconductor UART Figure 9 6 Transmit interrupt timing diagram ...

Page 152: ...152 246 152 246 ABOV Semiconductor AC30M1x64 1x32 SERIAL PERIPHERAL INTERFACE SPI CHAPTER 10 ...

Page 153: ...peration Programmable clock polarity and phase 8 9 16 17 bit wide transmit receive register 8 9 16 17 bit wide data frame Loop back mode Programmable start burst and stop delay time SPI Register Block Tx Data Register Rx Data Register Transmit Receive Logic Rx Shifter Tx Shifter Clock Divider Interrupt Generator APB DMA Req Tx Rx DMA En Ack Done Tx Rx TxData 16 0 RxData 16 0 TxSData 16 0 SPI DIV C...

Page 154: ...2 PIN DESCRIPTION 10 2 Table 10 1 External Pins PIN NAME TYPE DESCRIPTION SS I O SPI Slave select input output SCK I O SPI Serial clock input output MOSI I O SPI Serial data Master output Slave input MISO I O SPI Serial data Master input Slave output ...

Page 155: ...000_9000 Table 10 3 SPI Register Map NAME OFFSET TYPE DESCRIPTION RESET VALUE SP TDR 0x00 W SPI Transmit Data Register SP RDR 0x00 R SPI Receive Data Register 0x000000 SP CR 0x04 RW SPI Control Register 0x001020 SP SR 0x08 RW SPI Status Register 0x000006 SP BR 0x0C RW SPI Baud rate Register 0x0000FF SP EN 0x10 RW SPI Enable register 0x000000 SP LR 0x14 RW SPI delay Length Register 0x010101 ...

Page 156: ... 0 0 0 0 0 0 0x00000 RW 16 0 RDR Receive Data Register SP CR SPI Control Register 10 3 3 SP CR is a 20 bits read write register and can be set to configure SPI operation mode SP CR 0x4000_9004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXBC RXBC SSCIE TXIE RXIE SSMOD SSOUT LBE SSMARK SS0MO SS0POL MS MSBF CPHA CPOL BITSZ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 157: ...ect bit 0 SS output signal is disabled 1 SS output signal is enabled 8 SSPOL SS signal Polarity select bit 0 SS signal is Active Low 1 SS signal is Active High 5 MS Master Slave select bit 0 SPI is in Slave mode 1 SPI is in Master mode 4 MSBF MSB LSB Transmit select bit 0 LSB is transferred first 1 MSB is transferred first 3 CPHA SPI Clock Phase bit 0 Sampling of data occurs at odd edges 1 3 5 15 ...

Page 158: ...is inactive 1 SS signal is active 4 OVRF Receive Overrun Error flag 0 Receive Overrun error is not detected 1 Receive Overrun error is detected This bit is cleared by writing or reading SP RDR 3 UDRF Transmit Underrun Error flag 0 Transmit Underrun is not occurred 1 Transmit Underrun is occurred This bit is cleared by writing or reading SP TDR 2 TXIDLE Transmit Receive Operation flag 0 SPI is tran...

Page 159: ...e Register 10 3 5 SP BR is an16 bits read write register Baud rate can be set by writing the register SP BR 0x4000_900C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BR 0x00FF RW 15 0 BR Baud rate setting bits Baud Rate PCLK BR 1 BR must be bigger than 0 BR 2 ...

Page 160: ...SP EN 0x4000_9010 7 6 5 4 3 2 1 0 ENABLE 0 0 0 0 0 0 0 0 RW 0 ENABLE SPI Enable bit 0 SPI is disabled SP SR is initialized by writing 0 to this bit but other registers aren t initialized 1 SPI is enabled When this bit is written as 1 the dummy data of transmit buffer will be shifted To prevent this write data to SP TDR before this bit is active ...

Page 161: ... 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPL BTL STL 0 0 0 0 0 0 0 0 0x01 0x01 0x01 RW RW RW 23 16 SPL StoP Length value 0x01 0xFF 1 255 SCLKs SPL 1 15 8 BTL BursT Length value 0x01 0xFF 1 255 SCLKs BTL 1 7 0 STL STart Length value 0x01 0xFF 1 255 SCLKs STL 1 SS STL SPL BTL SCLK MISO MOSI MISO MISO MOSI MOSI Figure 10 2 SPI Wave form STL BTL and SPL ...

Page 162: ...of both device master and slave The nSS line is the slave select input of the slave The nSS pin of the master is not shown in the diagrams It has to be inactive by a high level on this pin if configured as input pin or by configuring it as an output pin The timing of a SPI transfer where CPHA is zero is shown in Figure 10 3 and 10 4 Two wave forms are shown for the SCK signal one for CPOL equals z...

Page 163: ...its inactive to its active state rising edge if CPOL equals zero and falling edge if CPOL equals one causes both the master and the slave to output the MSB of the byte in the SP TDR As shown in Figure 10 3 and 10 4 there is no delay of half a SCLK cycle The SCLK line changes its level immediately at the beginning of the first SCLK cycle The data on the input lines is read with the edge of the SCLK...

Page 164: ...164 246 164 246 ABOV Semiconductor AC30M1x64 1x32 I2 C Interface CHAPTER 11 ...

Page 165: ...communication speed Multi master bus configuration 7 bit addressing mode Standard data rate of 100 400 KBps STOP signal generation and detection START signal generation ACK bit generation and detection Figure 11 1 I 2 C Block diagram SDA F F 8 bit Shift Register SHFTR Slave Addr Register1 I2CSAR1 Noise Canceller debounce Data Out Register I2CDR I2CSCLHR I2CSCLLR I2CDAHR SDA Out Controller SCL Out ...

Page 166: ...emiconductor AC30M1x64 1x32 PIN DESCRIPTION 11 2 Table 11 1 I 2 C interface external pins PIN NAME TYPE DESCRIPTION SCL I O I 2 C channel Serial clock bus line open drain SDA I O I 2 C channel Serial data bus line open drain ...

Page 167: ...4000_A000 Table 11 3 I 2 C register map NAME OFFSET TYPE DESCRIPTION RESET VALUE IC DR 0x00 RW I 2 C Data Register 0xFF IC SR 0x08 R RW I 2 C Status Register 0x00 IC SAR 0x0C RW I 2 C Slave Address Register 0x00 IC CR 0x14 RW I 2 C Control Register 0x00 IC SCLL 0x18 RW I 2 C SCL LOW duration Register 0xFFFF IC SCLH 0x1C RW I 2 C SCL HIGH duration Register 0xFFFF IC SDH 0x20 RW I 2 C SDA Hold Regis...

Page 168: ...ata Register 11 3 1 IC DR is an 8 bits read write register It contains a byte of serial data to be transmitted or a byte which has just been received IC DR 0x4000_A000 7 6 5 4 3 2 1 0 ICDR 0xFF RW 7 0 ICDR The most recently received data or data to be transmitted ...

Page 169: ...eneral call detected or slave address ID byte was sent 6 TEND 1 Byte transmission complete flag 0 The transmission is working or not completed 1 The transmission is completed 5 STOP STOP flag 0 STOP is not detected 1 STOP is detected 4 SSEL Slave flag 0 Slave is not selected 1 Slave is selected 3 MLOST Mastership lost flag 0 Mastership is not lost 1 Mastership is lost 2 BUSY BUSY flag 0 I 2 C bus ...

Page 170: ...Address Register 11 3 3 IC SAR is an 8 bits read write register It shows the address in slave mode IC SAR 0x4000_A00C 7 6 5 4 3 2 1 0 SVAD GCEN 0x00 0 RW RW 7 1 SVAD 7 bit Slave Address 0 GCEN General call enable bit 0 General call is disabled 1 General call is enabled ...

Page 171: ...IF Interrupt status bit 0 Interrupt is inactive 1 Interrupt is active 5 SOFTRST Soft Reset enable bit 0 Soft Reset is disabled 1 Soft Reset is enabled 4 INTEN Interrupt enabled bit 0 Interrupt is disabled 1 Interrupt is enabled 3 ACKEN ACK enable bit in Receiver mode 0 ACK is not sent after receiving data 1 ACK is sent after receiving data 1 STOP Stop enable bit When this bit is set as 1 in transm...

Page 172: ... 3 5 IC SCLL is a 16 bit read write register SCL LOW time can be set by writing this register in master mode IC SCLL 0x4000_A018 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCLL 0xFFFF RW 15 0 SCLL SCL LOW duration value SCLL PCLK SCLL 15 0 2 PCLKs Default value is 0xFFFF Figure 11 3 SCL LOW Timing ...

Page 173: ...H is a 16 bit read write register SCL HIGH time will be set by writing this register in master mode IC SCLH 0x4000_A01C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCLH 0xFFFF RW 15 0 SCLH SCL HIGH duration value SCLH PCLK SCLH 15 0 3 PCLKs Default value is 0xFFFF Figure 11 4 SCL HIGH Timing ...

Page 174: ...SDH is a 15 bit read write register SDA HOLD time will be set by writing this register in master mode IC SDH 0x4000_A020 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDH 0x7FFF RW 14 0 SDH SDA HOLD time setting value SDH PCLK SDH 14 0 4 PCLKs Default value is 0x7FFF Figure 11 5 SDA HOLD Timing ...

Page 175: ...The data on the SDA line must be stable during the H period of the clock The H or L state of the data line can only change when the clock signal on the SCL line is L see Fig 11 6 Figure 11 6 I 2 C Bus bit transfer SCL SDA Data line Stable Data valid except S Sr P Change of Data allowed ...

Page 176: ...d to be free again a certain time after the STOP condition The bus is busy if a repeated START Sr is generated instead of a STOP condition In this respect the START S and repeated START Sr conditions are functionally identical For the remainder of this document therefore the S symbol will be used as a generic term to represent both the START and repeated START conditions unless Sr is particularly ...

Page 177: ...it can hold the clock line SCL L to force the master into a wait state Data transfer then continues when the slave is ready for another byte of data and releases clock line SCL A message which starts with such an address can be terminated by generation of a STOP conditions even during the transmission of a byte In this case no acknowledge is generated Figure 11 8 I 2 C Bus data transfer START or R...

Page 178: ...rate either a STOP condition to abort the transfer or a repeated START condition to start a new transfer If a slave receiver does acknowledge the slave address but sometime later in the transfer cannot receive any more data bytes the master must again abort the transfer This is indicated by the slave generating the not acknowledge on the first byte to follow The slave leaves the data line H and th...

Page 179: ...to start counting off their L period and once a device clock has gone L it will hold the SCL line in that state until the clock H state is reached see Figure 11 10 However the L to H transition of this clock may not change the state of the SCL line if another clock is still within its L by the device with the longest L period Devices with shorter L periods enter an H wait state during this time Wh...

Page 180: ...is determined by the winning master no information is lost during the arbitration process A master that loses the arbitration can generate clock pulses until the end of the byte in which it loses the arbitration If a master also incorporates a slave function and it loses arbitration during the addressing stage it s possible that the winning master is trying to address it The losing master must the...

Page 181: ...writing Master Transmitter 11 5 1 It shows the flow of transmitter in master mode see Figure 11 12 Figure 11 12 Transmitter Flowchart in Master mode From master to slave Master command or Data Write From slave to master ACK Interrupt SCL line is held low Interrupt after stop command P Arbitration lost as master and addressed as slave LOST Other master continues Master Receiver SLA W ACK DATA Rs ST...

Page 182: ...iver Flowchart in Master mode From master to slave Master command or Data Write From slave to master ACK Interrupt SCL line is held low Interrupt after stop command P ACK Arbitration lost as master and addressed as slave LOST Other master continues Master Transmitter SLA R ACK DATA Rs LOST LOST STOP LOST S or Sr SLA W Y N ACK STOP Y N LOST P P Sr IDLE ...

Page 183: ...re 11 14 Transmitter Flowchart in Slave mode SLA R ACK DATA LOST S or Sr Y ACK STOP Y N P IDLE IDLE Y GCALL From master to slave Master command or Data Write From slave to master ACK Interrupt SCL line is held low Interrupt after stop command P Arbitration lost as master and addressed as slave LOST General Call Address GCALL ...

Page 184: ...15 Figure 11 15 Receiver Flowchart in Slave mode SLA W ACK DATA LOST S or Sr Y N ACK STOP Y N P IDLE IDLE Y GCALL From master to slave Master command or Data Write From slave to master ACK Interrupt SCL line is held low Interrupt after stop command P Arbitration lost as master and addressed as slave LOST General Call Address GCALL ...

Page 185: ...185 246 ABOV Semiconductor Motor PWM MOTOR PULSE WIDTH MODULATOR CHAPTER 12 MPWM ...

Page 186: ...is mpwm counter clock source will be provided from SCU block The MPWM resolution and period will be defined by this MPWM clock configuration The default MPWM clock is same as RINGOSC clock Before enable MPWM module the proper MPWM clock selection should be required PERIOD DUTY UH DUTY UL DUTY VH DUTY VL DUTY WH DUTY WL DEAD TIME OVIN PRTIN APB BUS DEAD TIME GENERATOR PWM CONTROL MAIN COUNTER ADC T...

Page 187: ...E TYPE DESCRIPTION MPWMUH O MPWM Phase U H side output MPWMUL O MPWM Phase U L side output MPWMVH O MPWM Phase V H side output MPWMVL O MPWM Phase V L side output MPWMWH O MPWM Phase W H side output MPWMWL O MPWM Phase W L side output PRTIN I MPWM Protection Input OVIN I MPWM Over voltage Input ...

Page 188: ...L 0x0024 RW MPWM Duty WL register 0x0000_0001 MP CR1 0x0028 RW MPWM Control register 1 0x0000_0000 MP CR2 0x002C RW MPWM Control register 2 0x0000_0000 MP SR 0x0030 R MPWM Status register 0x0000_0000 MP IER 0x0034 RW MPWM Interrupt Enable 0x0000_0000 MP CNT 0x0038 R MPWM counter register 0x0000_0001 MP DTR 0x003C RW MPWM dead time control 0x0000_0000 MP PCR0 0x0040 RW MPWM protection 0 control reg...

Page 189: ...ime of H ch L channel become the inversion of H channel 10 1 channel symmetric mode Duty H decides toggle high low time of H ch L channel become the inversion of H channel 11 Not valid same with 00 0 UPDOWN 0 PWM Up count mode only available when MOTORB 1 1 PWM Up Down count mode This bit should be 1 if MOTORB 0 After initial PWM period and duty setting is completed the UAO bit should be set once ...

Page 190: ...utput L WLL 0 Normal Output L Active Output H 1 Normal Output H Active Output L VLL 0 Normal Output L Active Output H 1 Normal Output H Active Output L ULL 0 Normal Output L Active Output H 1 Normal Output H Active Output L The normal level is defined in each operating mode as below table Table 12 4 MPWM output Level setting PWM Output Level NORMAL mode MOTOR mode UP mode UPDOWN mode WH Default le...

Page 191: ...191 246 ABOV Semiconductor Motor PWM 0 1 WH CONTROL WH OUTPUT OLR WHL POLWH Figure 12 2 Polarity Control Block ...

Page 192: ...WHFL VHFL UHFL WLFL VLFL ULFL 0 0 0 0 0 0 0 0 RW RW RW RW RW RW 5 WHFL Select WH Output Force Level 0 1 Output Force Level is L Output Force Level is H 4 VHFL Select VH Output Force Level 0 1 Output Force Level is L Output Force Level is H 3 UHFL Select UH Output Force Level 0 1 Output Force Level is L Output Force Level is H 2 WLFL Select WL Output Force Level 0 1 Output Force Level is L Output F...

Page 193: ...should be set 1 Basically PRDIRQ and BOTIRQ are generated every period But the interrupt interval can be controlled from 0 to 8 periods When IRQN CR1 0 the interrupt is requested every period otherwise the interrupt is requested every IRQN 1 times of period MP CR2 MPWM Control Register 2 12 3 5 PWM Control Register 2 is 8 bit register MP CR2 0x4000_402C 7 6 5 4 3 2 1 0 HALT PSTART 0 0 0 0 0 0 0 0 ...

Page 194: ...egister 12 3 7 PWM UH channel duty register is 16 bit register MP DUH 0x4000_4010 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DUTY UH 0x0001 RW 15 0 DUTY UH 16 bit PWM Duty for UH output It should be larger than 0x0001 if Duty is 0x0000 PWM will not work MP DVH MPWM Duty VH Register 12 3 8 PWM VH channel duty register is 16 bit register MP DVH 0x4000_4014 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DUTY VH 0x...

Page 195: ... UL Register 12 3 10 PWM UL channel duty register is 16 bit register MP DUL 0x4000_401C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DUTY UL 0x0001 RW 15 0 DUTY UL 16 bit PWM Duty for UL output It should be larger than 0x0001 if Duty is 0x0000 PWM will not work MP DVL MPWM Duty VL Register 12 3 11 PWM VL channel duty register is 16 bit register MP DVL 0x4000_4020 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DUT...

Page 196: ... enable 5 WHIE ATR6IE WH Duty or ATR6 Match Interrupt enable 0 1 interrupt disable interrupt enable 4 VHIE ATR5IE VH Duty or ATR5 Match Interrupt enable 0 1 interrupt disable interrupt enable 3 UHIE ATR4IE UH Duty or ATR4 Match Interrupt enable 0 1 interrupt disable interrupt enable 2 WLIE ATR3IE WL Duty or ATR3 Match Interrupt enable 0 1 interrupt disable interrupt enable 1 VLIE ATR2IE VL Duty or...

Page 197: ...ar flag Duty interrupt is enabled if ATR5 was disabled 0 1 No interrupt occurred Interrupt occurred 3 DUHIF ATR4F PWM duty UH interrupt flag write 1 to clear flag Duty interrupt is enabled if ATR4 was disabled 0 1 No interrupt occurred Interrupt occurred 2 DWLIF ATR3F PWM duty WL interrupt flag write 1 to clear flag Duty interrupt is enabled if ATR3 was disabled 0 1 No interrupt occurred Interrupt...

Page 198: ... function 14 PSHRT Protect short condition This function is effective only for 2 channel symmetric mode For 1 channel mode never activated on both H side and L side at same time L side is always opposite of H side 0 1 Enable output short protection function Turn off both output when both H side and L side are active Disable output short protection function 8 DTCLK Dead time prescaler 0 1 Dead time...

Page 199: ...protection interrupt 5 WHPROTM Activate W phase H side protection output 0 1 Disable Protection Output Enable Protection Output with FOR value 4 VHPROTM Activate V phase H side protection output 0 1 Disable Protection Output Enable Protection Output with FOR value 3 UHPROTM Activate U phase H side protection output 0 1 Disable Protection Output Enable Protection Output with FOR value 2 WLPROTM Act...

Page 200: ...red Protection occurred or protection output enabled 4 VHPROT Activate V phase H side protection flag 0 1 Protection not occurred Protection occurred or protection output enabled 3 UHPROT Activate U phase H side protection flag 0 1 Protection not occurred Protection occurred or protection output enabled 2 WLPROT Activate W phase L side protection flag 0 1 Protection not occurred Protection occurre...

Page 201: ...R6 0x4000_406C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ATUDT ATMOD ATCNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 RW RW RW 19 ATUDT Trigger register update mode 0 1 ADC trigger value applied at period match event at the same time with period and duty registers update Trigger register update mode When this bit set written Trigger register values are sent to...

Page 202: ...ut signal Figure 12 1 PWM output generation chain Normal PWM UP Count mode timing 12 4 1 In normal pwm mode each channel is running independently 6 PWM output can be generated The example waveform is below figure Before PSTART is activated the PWM output will stay default value L When PSTART is enabled the period counter starts up count until MP PRD count value First period the MPWM does not gener...

Page 203: ... 4 3 The motor pwm operation has 3 kind of operating mode 2 Channel Symmetric mode 1 Channel Symmetric mode and 1 Channel Asymmetric mode The figure in below is for 2 channel symmetric mode waveform Figure 12 4 2 Channel Symmetric mode wave form MOTORB 0 MCHMOD 00 The default start level of both H side and L side is low For the H side pwm output level is changed to active level when the duty level...

Page 204: ...during down count period the L side DUTY register matching condition makes the default level pulse Figure 12 5 1 Channel Asymmetric mode wave form MOTORB 0 MCHMOD 01 The default start level of both H side and L side is low For the H side pwm output level is changed to active level when the H side duty level is matched in up count period and is returned to default level when the L side duty level i...

Page 205: ...eriod the H side DUTY register matching condition also makes the default level pulse Figure 12 6 1 Channel Symmetric mode wave form MOTORB 0 MCHMOD 10 The default start level of both H side and L side is low For the H side pwm output level is changed to active level when the H side duty level is matched in up count period and is returned to default level when the H side duty level is matched again...

Page 206: ...16 The pwm counter reached at duty value the pwm output is masked and dead time counter starts to run When dead time counter reached the value in DT 7 0 register the output mask is disabled Figure is an example of dead time operation in 1 channel symmetric mode Figure 12 7 PWM Dead time operation timing diagram Symmetric mode Below figure shows in case of 1 channel asymmetric mode operation Figure...

Page 207: ...time operate Norma dead time case is explained The dead time masking is activated at duty match time and the dead time counter runs When the dead time counter is reached to dead time value the mask is disabled Figure 12 9 Normal Dead time Operation TDUTY TDT A couple of figures in below show special case of dead time configurations ...

Page 208: ...2 11 Zero H side pulse timing TDT 2xTDUTY MASKED MASKED MP DUH V W MP CNT TDT Rising MP0UH MP0VH MP0WH MP0UH MP0VH MP0WH TDT Falling 2 x TDUTY DT Rising Mask DT Falling Mask MP PRD MASKED MASKED MP DUH V W MP0UH MP0VH MP0WH MP0UH MP0VH MP0WH MP CNT TDT Rising TDT Falling 2 x TDUTY DT Rising Mask DT Falling Mask MP PRD ...

Page 209: ... TDT Period TDUTY MAS KED MASKED MASKED MP DUH V W MP0UH MP0VH MP0WH MP0UH MP0VH MP0WH MP CNT TDT Rising TDT Falling TDT Falling 2 x TDUTY DT Rising Mask DT Falling Mask MP PRD MASKED MASKED MASKED MP DUH V W MP0UH MP0VH MP0WH MP0UH MP0VH MP0WH MP CNT TDT Rising TDT Falling TDT Falling 2 x TDUTY DT Rising Mask DT Falling Mask MP PRD ...

Page 210: ...5 L side always on TDUTY 0 dead time disabled MP DxH 0 MP CNT MP0UH MP0VH MP0WH MP0UH MP0VH MP0WH MP PRD No Rising mask No Falling mask Always Always L DT Rising Mask DT Falling Mask MP DxH MP PRD MP CNT MP0UH MP0VH MP0WH MP0UH MP0VH MP0WH DT Rising Mask DT Falling Mask MP PRD No Rising mask No Falling mask Always L Always ...

Page 211: ...iming In asymmetrical mode the wave from is not symmetric between and after the counter value being as period The duty compare of H side is performed in both up count period The duty compare of L side is performed in both down count period Figure 12 17 Asymmetrical PWM Timing and Sensing margin MP DUH V W MP0VH MP0VL MPxCNT MP0WH MP0WL MP0UH MP0UL MP DUL V W Data cannot be acquired MP DUL MP DUH M...

Page 212: ...register will make a trigger signal to start ADC conversion The conversion channel of ADC will be defined in ADC control register Figure 12 18 ADC Triggering function timing diagram ADC0_ST ADC1_ST PWM_V PWM_W PWM_U ADC_INT Max 6 ADC Triggering timing MP ATR1 MP ATR6 MP ATR registers are set by independently from the duty settings MP ATR2 MP CNT MP PRD MP ATR1 ...

Page 213: ...r PWM An example of ADC Data acquisition Figure 12 19 An example of ADC acquisition timing by event from MPWM MP DUH MP0V H MP0VL MP CNT MP0W H MP0WL MP0U H MP0UL MP DVH ADC Start MPxATR1 MPxCNT MP DWH ADC Start MP ATR1 ADC DMA Ia Ib ...

Page 214: ...214 246 214 246 ABOV Semiconductor AC30M1x64 1x32 Interrupt Generation Timing 12 4 10 Each timing event can make interrupt request to the CPU Figure 12 20 Interrupt Generation Timing ...

Page 215: ...215 246 ABOV Semiconductor Divider DIVIDER DIV64 CHAPTER 13 ...

Page 216: ...quential 64bit 32bit divider requires 32 clock cycles for one operation The equation of the operation is below AREGH AREGL BREG QREGH QREGL Unsigned 64bit dividend Unsigned 32bit divisor Unsigned 64bit quotient Unsigned 32bit remainder Unsigned 32 cycle operating time REGISTER INTERFACE DIVCON APB I F BREG QREGH QREGL AREGH AREGL REG BANK RREG a b Figure 13 1 Block Diagram ...

Page 217: ...PE DESCRIPTION RESET VALUE CR 0x0000 RW DIV control register 0x00000000 AREGL 0x0004 RW Most 32bit data register for dividend 0x00000000 AREGH 0x0008 RW Least 32bit data register for dividend 0x00000000 BREG 0x000C RW 32bit data register for divisor 0x00000000 QREGL 0x0010 R Most 32bit data register for quotient 0x00000000 QREGH 0x0014 R Least 32bit data register for quotient 0x00000000 RREG 0x001...

Page 218: ...e by zero flag 0 Not divide by zero 1 Divide by zero 9 BUSY Divider is now under operating 0 Divider is not busy 1 Divider is busy 8 DONE Divider operation done flag 0 Divider is now operating 1 Divider operation is done 4 MODE Start operation mode 0 START bit write operation will trigger the divide operation 1 BREG register write operation will trigger the divide operation 0 START Divide operatio...

Page 219: ...alue of dividend should be written this register AREGH 0x4000_0508 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AREGH 63 32 0x0000_0000 RW 31 0 AREGH High 32 bit value for dividend A BREG BREG Divisor Register 13 2 3 32bit value of divisor should be written this register When MODE bit set 1 the divide operation will be started automatically as soon as writi...

Page 220: ... QREG Quotient High 32bit Register 13 2 2 The divider will store high 32bit value of quotient in this register QREGH 0x4000_0514 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 QREGH 63 32 0x0000_0000 R 31 0 QREGH High 32 bit value for quotient RREG RREG Remainter Register 13 2 3 The divider will store 32bit value of remainter in this register RREG 0x4000_0518...

Page 221: ...221 246 ABOV Semiconductor 12 BIT A D Converter 12BIT A D CONVERTER CHAPTER 14 ...

Page 222: ...er supports 3 internal trigger sources supports Soft trig MPWM Timers Adjustable sample and hold time ADC IRQ ADC CONTROL 12 bit SAR ADC CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 TRIGGER CONTROL INTERRUPT CONTROL ADC DATA0 ADC DATA1 ADC DATA2 ADC DATA3 ADC DATA4 ADC DATA5 ADC DATA6 ADC DATA7 STSEL EOC PD S H CHSEL AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 CHANNEL SELECTION SOC MPWM...

Page 223: ...nal PIN NAME TYPE DESCRIPTION VDD P Analog Power 2 4V 5V VSS P Analog GND AN0 A ADC Input 0 AN1 A ADC Input 1 AN2 A ADC Input 2 AN3 A ADC Input 3 AN4 A ADC Input 4 AN5 A ADC Input 5 AN6 A ADC Input 6 AN7 A ADC Input 7 AN8 A ADC Input 8 AN9 A ADC Input 9 AN10 A ADC Input 10 AN11 A ADC Input 11 ...

Page 224: ...x0010 Reserved 0x0014 Reserved AD SCSR 0x0018 RW ADC Burst mode channel select 0x00 AD CR 0x0020 RW ADC Control register 0x00 AD SR 0x0024 RW ADC Status register 0x00 AD IER 0x0028 RW ADC Interrupt Enable register 0x00 0x002C Reserved AD DR0 0x0030 R ADCn Sequence 0 Data register 0x00 AD DR1 0x0034 R ADCn Sequence 1 Data register 0x00 AD DR2 0x0038 R ADCn Sequence 2 Data register 0x00 AD DR3 0x003...

Page 225: ...sequential conversion or 1 burst count 100 5st single sequential conversion or 5 burst count 001 2nd single sequential conversion or 2 burst counts 101 6st single sequential conversion or 6 burst counts 010 3rd single sequential conversion or 3 burst counts 110 7st single sequential conversion or 7 burst counts 011 4st single sequential conversion or 4 burst counts 111 8st single sequential conver...

Page 226: ...CH s channel by AD TRG SEQTRG in Single sequential mode AD starts conversion the AD SCSR SEQ CH s channel by AD TRG BSTTRG in Burst mode 0000 Current Sequence is 0 the AD SCSR SEQ0CH s channel is converted by AD TRG SEQTRG0 in Single sequential mode or by AD TRG BSTTRG in Burst mode 0001 Current Sequence is 1 0010 Current Sequence is 2 0011 Current Sequence is 3 0100 Current Sequence is 4 0101 Cur...

Page 227: ...ble to save power Don t set 1 here it s optional bit 14 8 CLKDIV 6 0 ADC clock divider when EXTCLK is 0 ADC clock system clock CLKDIV CKDIV 0 ADC clock system clock CKDIV 1 ADC clock stop 7 ADCPD ADC Power Down 0 ADC normal mode 1 ADC Power Down mode 6 EXTCLK Select if ADC uses external clock 0 internal clock CKDIV enabled 1 external clock SCU clock MCCR7 5 CLKINVT Divided clock inversion optional...

Page 228: ...2 SEQTRG1 SEQTRG0 BSTTRG 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 31 28 SEQTRG7 8 th Sequence Trigger Source 27 24 SEQTRG6 7 th Sequence Trigger Source 23 20 SEQTRG5 6 th Sequence Trigger Source 19 16 SEQTRG4 5 th Sequence Trigger Source 15 12 SEQTRG3 4 th Sequence Trigger Source 11 8 SEQTRG2 3 rd Sequence Trigger Source 7 4 SEQTRG1 2 nd Sequence Trigger Sour...

Page 229: ... conversion sequence channel selection 11 8 SEQ2CH 3 rd conversion sequence channel selection 7 4 SEQ1CH 2 nd conversion sequence channel selection 3 0 SEQ0CH 1 st conversion sequence channel selection This channel should be used for Single mode AD CR ADC Control Register 14 3 6 ADC start register This register is 8 bit register AD CR 0x4000_B020 7 6 5 4 3 2 1 0 ASTOP ASTART 0 0 WO RW 7 ASTOP 0 No...

Page 230: ...set at the end of a burst conversion or a sequence convrersion set Write 1 to clear flag Sequence conversion set is the operation that AD converts to AD MR SEQCNT 0 None 1 End of Sequence Interrupt occurred in burst or single sequential mode 0 EOCIRQ This flag will be set upon each conversion in a single is occurred Write 1 to clear flag 0 None 1 End of Conversion Interrupt occurred AD IER Interru...

Page 231: ...isters are 16 bit registers ADC conversion result register AD DR0 0x4000_B030 AD DR1 0x4000_B034 AD DR2 0x4000_B038 AD DR3 0x4000_B03C AD DR4 0x4000_B040 AD DR5 0x4000_B044 AD DR6 0x4000_B048 AD DR7 0x4000_B04C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADC DATA 0x000 R 15 4 ADC DATA ADC channel 0 7 data 12 bit ...

Page 232: ... MR ADMOD is 0x0 and AD MR SEQCNT is 0x0 ADC conversion will be started by AD CR ASTART written as 1 Once AD CR ASTART is set SOC start of Conversion will be activated in 3 ADC clocks and AD SR EOCIRQ will be set in 2 ADC clocks and 2 PCLKs after the End of Conversion Figure 14 1 ADC Single mode timing when ADCn MR AMOD 0 ...

Page 233: ...TART When AD MR TRGSEL is set as timer event trigger or mpwm event trigger SOC will be made by the trigger of AD TRG BSTTRG AD TRG 3 0 For example ADC conversion will be started by the trigger of TIMER3 if AD TRG BSTTRG is set as TIMER3 Once the BSTTRG s trigger events ADC will covert ADC Channels as much as AD MR SEQCNT set See Figure 14 4 Figure 14 2 ADC Burst mode timing when AD MR AMOD 1 Figur...

Page 234: ... sequential conversion mode AD MR AMOD is 2 b00 and AD MR SEQCNT is not 2 b00 The operation of sequential mode is the almost same as the burst mode The difference is ths source of SOC Each SOC is made by the trigger of the SEQTRGx as each SEQCNT See figure 14 6 Figure 14 4 ADC Sequential mode timing when AD MR AMOD 0 and AD MR SEQCNT 0 Figure 14 5 ADC trigger timing in sequential mode SEQCNT 3 b11...

Page 235: ...235 246 ABOV Semiconductor CHARACTERISTIC SECTION 3 CHARACTERISTIC ...

Page 236: ...236 246 236 246 ABOV Semiconductor AC30M1x64 1x32 Electrical Characteristic CHAPTER 1 ...

Page 237: ...ximum rating Parameter Symbol min max unit Power Supply VDD VDD 0 5 6 V Analog Power Supply AVDD AVDD 0 5 6 V VDC Output Voltage VDD18 V Input High Voltage VDD 0 5 V Input Low Voltage VSS 0 5 V Output Low Current per pin IOL 5 mA Output Low Current Total IOL TBD mA Output High Current per pin IOH 5 mA Output Low Current Total IOH TBD mA Power consumption mW Input Main Clock Range 4 16 MHz Operatin...

Page 238: ... MHz SOSC 32 768 kHz HSI 38 8 40 41 2 MHz LSI 32 40 48 kHz Operating Temperature Top Top 40 105 Table 1 3 DC Electrical Characteristics VDD 5V Ta 25 Parameter Symbol Condition Min Typ Max unit Input Low Voltage VIL Schmitt input 0 2VDD V Input High Voltage VIH Schmitt input 0 8VDD V Output Low Voltage VOL IOL 3mA VSS 1 0 V Output High Voltage VOH IOH 3mA VDD 1 0 V Input High Leakage IIH 4 uA Input...

Page 239: ...SC RUN HSIOSC RUN SXOSC STOP MXOSC STOP HCLK RUN TBD mA PowerDown Mode IDDSTOP LSIOSC STOP HSIOSC STOP SXOSC STOP MXOSC STOP HCLK STOP 5 10 uA note uart en 1 port toggle 5V POR Electrical Characteristics 1 1 4 Table 1 5 POR Electrical Characteristics Temperature 40 105 Parameter Symbol Condition Min Typ Max unit Operating Voltage VDD18 1 6 1 8 2 0 V Operating Current IDDPoR Typ 6uA If always on 60...

Page 240: ... V LVD Set Level 1 VLVD1 VDD falling slow 2 4 2 65 3 1 V LVD Set Level 2 VLVD2 VDD falling slow 3 55 3 7 4 15 V LVD Set Level 3 1 VLVD3 VDD falling slow 4 2 4 35 4 8 V CAUTION 1 This LVD Voltage level is not recommanded Because it sometimes can change LVD detect level at high temperature VDC Electrical Characteristics 1 1 6 Table 1 7 VDC Electrical Characteristics Temperature 40 105 Parameter Symb...

Page 241: ...haracteristics 1 1 7 Table 1 8 External OSC Characteristics Temperature 40 105 Parameter Symbol Condition Min Typ Max unit Operating Voltage VDD 2 2 5 5 V IDD 4MHz 5V 240 uA Frequency OSCFreq 4 16 MHz Output Voltage OSCVOUT 1 2 2 4 V Load Capacitance LOADCAP 5 22 35 pF ...

Page 242: ...erature 40 105 Parameter Symbol Condition Min Typ Max unit Operating Voltage AVDD 2 4 5 5 5 V Resolution 12 Bit Operating Current IDDA 2 8 mA Analog Input Range 0 AVDD V Conversion Rate 1 0 MSPS Operating Frequency ACLK 16 MHz DC Accuracy INL 3 5 LSB DNL 2 5 LSB Offset Error 1 5 LSB Full Scale Error 1 5 LSB SNDR SNDR 68 dB THD 70 dB ...

Page 243: ...243 246 ABOV Semiconductor Package Package CHAPTER 2 ...

Page 244: ...244 246 244 246 ABOV Semiconductor AC30M1x64 1x32 LQFP 48 Package dimension 2 1 Figure 2 1 Package dimension LQFP 48 ...

Page 245: ...245 246 ABOV Semiconductor Package LQFP 32 Package dimension 2 2 Figure 2 2 Package dimension LQFP 32 ...

Page 246: ...246 246 246 246 ABOV Semiconductor AC30M1x64 1x32 QFN 32 Package dimension 2 3 Figure 2 3 Package dimension QFN 32 ...

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