Abov AC30M1x32, User Manual, Page: 111 / 246

111 / 246
ABOV Semiconductor
Watch-Dog Timer
Functional Description 6.3
The watchdog timer Count can be enabled by WDTEN (WDT.CON[4]) to ‘1’. As watchdog timer is enabled, the down
counter will start counting from the Load Value. If WDTRE (WDT.CON[6]) is set as ‘1’, WDT reset would be asserted when
the WDT counter value reached to ‘0’ (underflow event) from WDT.LR value. Before WDT counter down to 0, software can
write a certain value to register WDT.LR to reload WDT counter.
Timing diagram 6.3.1
Figure 6.2 Timing diagram in interrupt mode operation when WDT clock is external clock
In WDT interrupt mode, once WDT underflow occurred then a certain count value would be reloaded to prevent next
WDT interrupt in short time period and this reloading action only be activated when the watchdog timer counter set to be
Interrupt mode(set WDTIE of WDT.CON). It takes up to 5 cycles from Load value to the CNT value. The WDT interrupt
signal and CNT value data might be delayed maximum by 2 system bus clocks in synchronous logic.
Prescale Table 6.3.2
The WDT includes a 32-bit down counter with programmable pre-scaler to define different time-out intervals.
The clock sources of watchdog timer can be peripheral clock (PCLK) or one of 5external clock sources. External clock
source can be enable by CKSEL (WDT.CON[3]) set to ‘1’ and External clock source was chosen in MCCR3 register of SCU
(system control unit) block.
To make WDT counter base clock, user can control 3-bit pre-scaler WPRS [2:0] in WDT.CON register and the maximum
pre-scaled value is “clock source frequency/256”. The pre-scaled WDT counter clock frequency values are listed in
following table.
Selectable clock source (40 kHz ~ 16 MHz) and the time out interval when 1 count
Time out period = {(Load Value) * (1/pre-scaled WDT counter clock frequency) + max 5Text} + max 4Tclk
*Time out period (time out period from load Value to interrupt set ‘1’)