Abov AC30M1x32, User Manual, Page: 12 / 246

12 / 246
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AC30M1x64/1x32
ABOV Semiconductor
Functional Description 1.3.2
The following section provides an overview of the features of AC30M1x64/1x32 microcontroller.
ARM Cortex-M0
ARM powered Cortex-M0 Core based on ARMv6M architecture which is optimized for small size and low power system.
On core system timer (SYSTICK) provides a simple 24-bit timer easy to manage the system operation
Thumb-compatible Thumb-2 only instruction set processor core makes code high-density.
Hardware division and single-cycle multiplication is present
Integrated Nested Vectored Interrupt Controller (NVIC) provides deterministic interrupt handling.
SWD debugging features are provided.
Max 40MHz operating frequency with one wait execution
Nested Vector-Interrupt Controller (NVIC)
The ARM Nested Vectored Interrupt Controller (NVIC) on the ARM Cortex-M0 core is included which handles all the
internal and external exceptions. When interrupt condition is detected, the processor state is automatically stored to the
stack and automatically restored from the stack at the end of interrupt service routine.
The vector is fetched in parallel to the state saving, which enables efficient interrupt entry.
The processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of
state saving and restoring.
64/32KB Internal Code Flash Memory
The AC30M1x64/1x32 provides internal 64/32KB code flash memory and its controller. This is enough to program motor
algorithm and general control the system. Self-programming is available and ISP and SWD programming is also supported
in boot or debugging mode.
Instruction and data cache buffer are present and overcome the low bandwidth flash memory. The CPU can access flash
memory with one wait state up to 40 MHz bus frequency.
4KB 0-wait Internal SRAM
On chip 4KB 0-wait SRAM can be used for working memory space and program code can be loaded on this SRAM.
Boot Logic
The smart boot logic supports the flash programming. The AC30M1x64/1x32 can be entered by external boot pin and
UART and SPI programming are available in boot mode. UART0 or SPI is used in boot mode communication.
System Control Unit (SCU)
The SCU block manages internal power, clock, reset and operation mode. It also controls analog blocks (Oscillator Block,
VDC and BOD (LVD))
32-bit Watchdog Timer (WDT)
The watchdog timer performs system monitoring function. It will generate internal reset or interrupt to notice abnormal
status of the system.
Multi-purpose 16-bit Timer
Four-channel 16-bit general purpose timers supports below functions.
- Periodic timer mode - Counter mode
- PWM mode - Capture mode
Built-in timer also supports counter-synchronization mode can generate synchronized waves and timing.