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Publication No. 500-9300875565-000 Rev. C.0

Programming 61

3.3.9 Network Interrupt Command Register

Network Interrupt Command (NIC) BAR2 (Offset $1D): An 8-bit register
containing a four-bit code that defines the type of network interrupt issued. See

Table 3-46

on page 61 for a definition of the possible codes. The NIC is both read

and write accessible. Only writing to the NIC register will initiate the network
interrupt. The network interrupt is transmitted in order following after all
previously written data.

The NTD, NTN and the NIC registers described above are used to generate
network interrupts. Four pairs of registers described below are involved with
receiving those network interrupts.

3.3.10 Interrupt 1 Sender Data FIFO

Interrupt 1 Sender Data FIFO (ISD1) BAR2 (Offset $20): A 32-bit FIFO containing
up to 127 Dwords of data, which has been sent to this node in type 1 network
interrupt packets. The function of the 32 bits of data is user defined. The ISD1 is a
127 location deep FIFO, but it is coupled and slaved to the companion FIFO SID1.
Essentially, there is only one address pointer for both FIFOs and that pointer is
only affected by access to the SID1 FIFO. For this reason, each location within the
data (ISD1) FIFO can be read multiple times without incrementing the address
pointer, while reading the companion SID1 FIFO increments the pointer for both
FIFOs. For this same reason, the user must read the data (ISD1) before the Sender
ID (SID1) or the corresponding data will be lost.

Table 3-46 Network Interrupt Command Register

NIC: BAR2 Offset $1D

NIC[3,2,1,0] Function
X000

Reset Node Request (sets LISR Bit 03 only, the user

application must perform the actual reset

X001

Network Interrupt 1 (stored in a 127 deep FIFO at the receiving

node)

X010

Network Interrupt 2 (stored in a 127 deep FIFO at the receiving

node)

X011

Network Interrupt 3 (stored in a 127 deep FIFO at the receiving

node)

X100

Reserved (Setting to this type will only set the OWN DATA bit in

the LCSR1)

X101

Reserved (Setting to this type will only set the OWN DATA bit in

the LCSR1)

X110

Reserved (Setting to this type will only set the OWN DATA bit in

the LCSR1)

X111

Network Interrupt 4 (stored in a 127 deep FIFO at the receiving

node)

1XXX

Global enable. Send to all nodes regardless of NTN Register

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Summary of Contents for PCIE-5565RC Series

Page 1: ...erutilized and idle equipment along with credit for buybacks and trade ins Custom engineering so your equipment works exactly as you specify Critical and expedited services Leasing Rentals Demos In stock Ready to ship TAR certified secure asset solutions Expert team I Trust guarantee I 100 satisfaction All trademarks brand names and brands appearing herein are the property of their respective owne...

Page 2: ...with Interrupts THE PCIE 5565RC IS DESIGNED TO MEET THE EUROPEAN UNION EU RESTRICTION OF HAZARDOUS SUBSTANCE ROHS DIRECTIVE 2002 95 EC CURRENT REVISION Publication No 500 9300875565 000 Rev C 0 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 3: ...Systems is registered with an approved Producer Compliance Scheme PCS and subject to suitable contractual arrangements being in place will ensure WEEE is processed in accordance with the requirements of the WEEE Directive Abaco Systems will evaluate requests to take back products purchased by our customers before August 13 2005 on a case by case basis A WEEE management fee may apply Artisan Techno...

Page 4: ...s a hexadecimal number following the C programming language convention Thus One dozen 12D 0x0C 1100b The multipliers k M and G have their conventional scientific and engineering meanings of x103 x106 and x109 respectively The only exception to this is in the description of the size of memory areas when k M and G mean x210 x220 and x230 respectively NOTE When describing transfer rates k M and G mea...

Page 5: ... Box 14070 Portland OR 97214 800 433 5177 U S 503 797 4207 International 503 234 6762 FAX PCI Express Base Specification Revision 1 0a April 15 2003 Intel 41110 Serial to Parallel PCI Bridge Developer s Manual 310183 001US April 2006 For information on PLD Applications PCI X IP Core contact them at United States PLD Applications Inc 2570 North First St 2nd floor San Jose CA 95131 1036 408 273 4530...

Page 6: ...zation RMA form available via the website Embedded Support page LINK www abaco com embedded support Do not return products without first contacting the Abaco Repairs facility Compliance This chapter provides the applicable information regarding regulatory compliance for the PCIE 5565RC Abaco s PCIE 5565RC has been evaluated and has met the requirements for compliance to the following standards BS ...

Page 7: ...device pursuant to Part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instruction manual may cause harmful interference to radio communications Operation of ...

Page 8: ... Atmosphere Do not operate the system in the presence of flammable gases or fumes Operation of any electrical system in such an environment constitutes a definite safety hazard Keep Away from Live Circuits Operating personnel must not remove product covers Component replacement and internal adjustments must be made by qualified maintenance personnel Do not replace components with power cable conne...

Page 9: ... any host processor A block diagram of the PCIE 5565RC is shown in Figure 1 on page 10 Features Features include High speed easy to use fiber optic network 2 12 Gbaud serially x4 lane PCI Express 1 0a to PCI Bridge No host processor involvement in the operation of the network Selectable Redundant Mode of Operation Up to 256 nodes Connectivity with multimode fiber up to 300 m singlemode fiber up to...

Page 10: ...sign flexibility and improved performance over the classic VMIPCI 5565 in at least three areas 1 The PCIE 5565RC s DMA burst and PIO write access rates have an improvement over the classic VMIPCI 5565 2 The PCIE 5565RC s access bandwidth for the onboard SDRAM memory has doubled improving the overall throughput 3 The PCIE 5565RC is field upgradeable as new features are added The classic VMIPCI 5565...

Page 11: ... Fiber Optic Reflective Memory with Interrupts Publication No 500 9300875565 000 Rev C 0 Block Diagram Figure 1 Block Diagram of PCIE 5565RC Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 12: ...Publication No 500 9300875565 000 Rev C 0 About This Manual 11 Figure 2 Typical Reflective Memory Network Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 13: ...Configuration 18 1 4 Physical Installation 21 1 5 Front Panel Description 22 1 5 1 LED Description 23 1 6 Cable Configuration 23 1 6 1 Connector Specification Singlemode and Multimode 23 2 Theory of Operation 26 2 1 Basic Operation 26 2 2 Front Bezel LED Indicators 26 2 3 RFM 5565 Register Sets 27 2 4 Reflective Memory RAM 27 2 5 Interrupt Circuits 28 2 6 Network Interrupts 30 2 7 Redundant Transf...

Page 14: ...IFO 62 3 3 14 Interrupt 3 Sender Data FIFO 62 3 3 15 Interrupt 3 Sender ID FIFO 62 3 3 16 Interrupt 4 Sender Data FIFO 62 3 3 17 Interrupt 4 Sender ID FIFO 62 3 4 Example of a Block DMA Operation for RFM 5565 64 3 5 Example of a Scatter Gather DMA Operation for RFM 5565 65 3 6 Example of a PCI PIO Sliding Window Operation for RFM 5565 67 3 7 Example of Network Interrupt Handling 68 3 7 1 Setup 68 ...

Page 15: ... and S2 Location PCIE 5565RC 20 Figure 1 2 Installing the PCIE 5565RC 21 Figure 1 3 Front Panel of PCIE 5565RC 22 Figure 1 4 LC Type Fiber Optic Cable Connector 24 Figure 1 5 Example Six Node Ring Connectivity PCIE 5565RC 25 Figure 2 1 Interrupt Circuitry Block Diagram 29 Figure 3 1 Block Diagram of the Network Interrupt Reception Circuitry 63 Artisan Technology Group Quality Instrumentation Guara...

Page 16: ...Table 3 16 PCI Base Address Register 5 41 Table 3 17 PCI Cardbus CIS Pointer Register 41 Table 3 18 PCI Subsystem Vendor ID Register 41 Table 3 19 PCI Subsystem ID Register 42 Table 3 20 PCI Expansion ROM Base Register 42 Table 3 21 PCI Capability Pointer Register 43 Table 3 22 PCI Interrupt Line 43 Table 3 23 PCI Interrupt Pin 43 Table 3 24 PCI Min_Gnt 43 Table 3 25 PCI Max_Lat 44 Table 3 26 Loca...

Page 17: ...ddress Remap 50 Table 3 42 Memory Map of the Local Control and Status Registers 52 Table 3 43 Local Control and Status Register 1 53 Table 3 44 Local Interrupt Status Register 57 Table 3 45 Local Interrupt Enable Register 60 Table 3 46 Network Interrupt Command Register 61 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 18: ...ard s heat damage and other visible contamination All claims arising from shipping damage should be filed with the carrier and a complete report sent to Abaco Systems Customer Care 1 2 Handling Precaution Some of the components assembled on Abaco s products may be sensitive to electrostatic discharge and damage may occur on boards that are subjected to a high energy electrostatic field When the bo...

Page 19: ...nodes are configured with Rogue Master 0 enabled and that data will be lost NOTE No more than one node on the ring should be configured with Rogue Master 1 enabled Certain packets will be removed from the ring when two or more nodes are configured with Rogue Master 1 enabled and that data will be lost Prior to installing the RFM 5565 in the host system switch S1 must be configured for the appropri...

Page 20: ...OFF OFF OFF 8 8 OFF OFF OFF OFF OFF ON OFF OFF 4 4 OFF OFF OFF OFF OFF OFF ON OFF 2 2 OFF OFF OFF OFF OFF OFF OFF ON 1 1 OFF OFF OFF OFF OFF OFF OFF OFF 0 0 Factory Default S2 positions 1 through 8 OFF Table 1 2 Switch S1 Configuration RFM 5565 Position 1 OFF non redundant mode Position 1 ON redundant mode Position 2 OFF higher performance achievable Position 2 ON low network usage Position 5 OFF ...

Page 21: ...Speed Fiber Optic Reflective Memory with Interrupts Publication No 500 9300875565 000 Rev C 0 Figure 1 1 S1 and S2 Location PCIE 5565RC Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 22: ...e ID has been set prior to installation Also setup the board for the desired mode of operation See Section Switch S1 and S2 Configuration on page 18 2 Install the PCIE 5565RC firmly into the PCIe connector refer to Figure 1 2 below for installation of the PCIE 5565RC Install the screw to secure the PCIE 5565RC to the chassis 3 Close the system chassis apply power Figure 1 2 Installing the PCIE 556...

Page 23: ... TX is the transmitter The PCIE 5565RC uses LC type fiber optic cables Figure 1 3 Front Panel of PCIE 5565RC CAUTION When fiber optic cables are not connected the supplied dust caps need to be installed to keep dust and dirt out of the optics Do not power up the PCIE 5565RC without the fiber optic cables installed This could cause eye injuries TX RX STATUS SIG DET OWN DATA STATUS RX RECEIVER CONNE...

Page 24: ... illustration of the LC type multimode or singlemode fiber optic connector 1 6 1 Connector Specification Singlemode and Multimode Compatible with LC standard and JIS C 5973 compliant Ceramic ferrule Temperature range 20 C to 85 C Table 1 3 LED Descriptions LED Color Description Status Red User defined board status indicator SIG DET Yellow Indicates optical network connection Own Data Green Indicat...

Page 25: ...e Memory with Interrupts Publication No 500 9300875565 000 Rev C 0 Figure 1 4 LC Type Fiber Optic Cable Connector 0 84 21 23 0 49 1 25 Dimensions inches mm 4 5mm Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 26: ...on No 500 9300875565 000 Rev C 0 Handling and Installation 25 Figure 1 5 Example Six Node Ring Connectivity PCIE 5565RC Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 27: ...a write to onboard SDRAM from the host system The write can be as simple as a PIO target write or it can be due to a DMA cycle by the resident DMA engine While the write to the SDRAM is occurring circuitry on the RFM 5565 automatically writes the data and other pertinent information into the transmit FIFO From the transmit FIFO the transmit circuit retrieves the data and puts it into a variable le...

Page 28: ...cal Configuration Registers Base Address Register 0 has the starting address for register memory space accesses and Base Address Register 1 has the starting address for register IO space accesses Some Local Configuration Registers pertinent to the RFM 5565 s operation include the Interrupt Control and Status Register INTCSR and the DMA Control Registers RFM Control and Status Registers The RFM Con...

Page 29: ...terrupt Input LINTi The primary tier interrupt source 1 is used during DMA cycles and must be configured in the DMA registers The other primary tier interrupt source 2 is the Local Interrupt Input LINTi All secondary tier interrupts are funneled through the LINTi Second tier interrupts include several operational status bits faults and network interrupts The second tier interrupts are selected and...

Page 30: ... LINT Second Tier Interrupts Interrupt Control and Status Register INTSCR Offset 68 Bits 11 and 15 DMA 0 Done Bits 18 and 21 Primary Tier Interrupts Host Interrupt INTA RFM Control and Status Registers per Base Address Register 2 Offset 14 RFM Control and Status Registers per Base Address Register 0 or 1 Local Interrupt Enable Register LIER Artisan Technology Group Quality Instrumentation Guarante...

Page 31: ...Instead it sets a bit in the LISR register which will result in a PCI interrupt if enabled The actual board reset should be performed by the host system in an orderly fashion However the user application could use this network interrupt for any purpose 2 7 Redundant Transfer Mode of Operation The RFM 5565 is capable of operating in a redundant transfer mode The board is configured for redundant mo...

Page 32: ...onment Normally the solution is to isolate and replace the malfunctioning board and or improve the environment However some users prefer to tolerate sporadic rogue packets rather than halt the system for maintenance provided the rogue packets are removed from the network To provide tolerance for rogue packet faults the RFM 5565 contains circuitry that allows it to operate as one of two Rogue Maste...

Page 33: ...and the Reflective Memory The location of the register sets and the Reflective Memory varies from system to system and can even vary from slot to slot within a system For operations beyond the basic setup such as enabling or disabling interrupts or performing DMA cycles the user must know the specific bit assignments of the registers within the three register sets That information is provided in t...

Page 34: ...can be accessed as either Byte Word or Double word request Table 3 1 PCI Configuration Registers Address Hex 31 24 23 16 15 8 7 0 00 Device ID Vendor ID 04 Status Register Command Register 08 Class Code Revision ID 0C BIST Header Type Latency Timer Cache Line Size 10 Base Address Register 0 14 Base Address Register 1 18 Base Address Register 2 1C Base Address Register 3 20 Base Address Register 4 ...

Page 35: ...ed Yes No 0 4 Reserved N A N A 0 5 VGA Palette Snoop Not Supported Yes No 0 6 Parity Error Response Writing a zero 0 indicates parity error is ignored and the operation continues Writing a one 1 indicates parity checking is enabled Yes Yes 0 7 Wait Cycle Control Controls whether a device does address data stepping A zero 0 indicates the device never does stepping A one 1 indicates the device alway...

Page 36: ... 0 Yes No 0 8 Master Data Parity Error Detected Set by the Reflective Memory acting as a master when it detects a data parity error if parity error response bit is set Yes Yes Clr 0 10 9 DEVSEL Timing Hardwired to Binary 10 Devsel timing is slow Yes No 10 11 Target Abort When set to one 1 indicates the Reflective Memory has signaled a Target Abort Writing a one 1 clears this bit to zero 0 Yes Yes ...

Page 37: ... PCI Class Code Register PCI Class Code Offset 09 Bit Description Read Write Value after PCI Reset 7 0 Register Level Programming Interface None defined Yes No 0 15 8 Subclass Code Yes No 80 23 16 Base Class Code Yes No 02 Base Class Code of 02 equals Network Controller Subclass Code of 80 equals other network controller Table 3 7 PCI Cache Line Size Register PCI Cache Line Size Offset 0C Bit Desc...

Page 38: ...s multiple functions Writing a zero 0 indicates single function Yes No 0 Table 3 10 PCI Built in Self Test Register PCI Built in Self Test Offset 0F Bit Description Read Write Value after PCI Reset 3 0 BIST Pass Failed Writing 0 indicates a device passed its test Non 0 values indicate a device failed its test Device specific failure codes can be encoded in a non 0 value Yes No 0 5 4 Reserved Yes N...

Page 39: ...1 indicates the register maps into I O Space NOTE Hardcoded to zero 0 Yes No 0 2 1 Register Location Values 00 Locate anywhere in 32 bit Memory Address Space 01 Locate below 1 MByte Memory Address Space 10 Locate anywhere in 64 bit Memory Address Space 11 Reserved NOTE Hardcoded to 00 Yes No 00 3 Prefetchable Writing a one 1 indicates there are no side effects on reads NOTE Hardcoded to zero 0 Yes...

Page 40: ...ase Address for I O access to Local Configuration registers requires 256 bytes NOTE Hardcoded to 0 Yes No 0 31 8 I O Base Address I O Base Address for access to Local Configuration registers Yes Yes 0 NOTE This register will be altered by the system BIOS during the system boot process Table 3 13 PCI Base Address Register 2 for Access to RFM Control and Status Registers PCIBAR2 Offset 18 Bit Descri...

Page 41: ...e 3 14 PCI Base Address Register 3 for Access to Reflective Memory PCIBAR3 Offset 1C Bit Description Read Write Value after PCI Reset 0 Memory Space Indicator Writing zero 0 indicates the register maps into Memory Space Writing a one 1 indicates the register maps into I O Space Yes No 0 2 1 Register Location Values 00 Locate anywhere in 32 bit Memory Address Space 01 Locate below 1 MByte Memory Ad...

Page 42: ...Bit Description Read Write Value after PCI Reset 31 0 Reserved Yes No 0 Table 3 16 PCI Base Address Register 5 PCIBAR5 Offset 24 Bit Description Read Write Value after PCI Reset 31 0 Reserved Yes No 0 Table 3 17 PCI Cardbus CIS Pointer Register PCI Cardbus CIS Pointer Offset 28 Bit Description Read Write Value after PCI Reset 31 0 Cardbus Information Structure Pointer for PCMCIA Not Supported Yes ...

Page 43: ...ion ROM Base Offset 30 Bit Description Rea d Write Value after PCI Reset 0 Address Decode Enable A one 1 indicates a device accepts accesses to the Expansion ROM address A zero 0 indicates a device does not accept accesses to Expansion ROM space Should be set to zero 0 if there is no Expansion ROM Works in conjunction with EROMRR 0 Yes No 0 10 1 Reserved Yes No 0 31 1 1 Expansion ROM Base Address ...

Page 44: ...ected to each interrupt line of the device Yes Yes 0 NOTE This register will be altered by the system BIOS during the system boot process Table 3 23 PCI Interrupt Pin PCI Interrupt Pin PCIIPR Offset 3D Bit Description Read Write Value after PCI Reset 7 0 Interrupt Pin Register Indicates which interrupt pin the device uses The following values are decoded the Reflective Memory supports only INTA 1 ...

Page 45: ...ax_Lat PCIMLR Offset 3F Bit Description Read Write Value after PCI Reset 7 0 Max_Lat Specifies how often the device must gain access to the PCI bus Value is a multiple of μsec increments Yes No 0 Table 3 26 Local Configuration and DMA Control Registers PCI Offset from Base Address Register Name Writable 00 07 Reserved N A 08 MARBR same as AC Y 0C Big Little Endian Descriptor Y 10 67 Reserved N A 6...

Page 46: ...erates in Delayed Transaction mode for PCI reads The RFM 5565 issues a retry to the PCI Host and fetches read data Yes Yes 0 25 Reserved Yes No 1 31 26 Reserved Yes No 00 Table 3 28 Big Little Endian Descriptor Register BIGEND BAR0 1 Offset 0C Bit Description Read Write Value after PCI Reset 4 0 Reserved Yes No 00 5 PCI PIO RFM Address Space Big Endian Mode Address Invariance Writing a one 1 speci...

Page 47: ... Reset 7 0 Reserved Yes No 00 8 PCI Interrupt Enable Writing a one 1 enables PCI interrupts Yes Yes 1 10 9 Reserved Yes No 0 11 Local Interrupt Input Enable Writing a one 1 enables a local interrupt i e RFM interrupts to assert a host Interrupt Yes Yes 0 14 12 Reserved Yes No 0 15 Local Interrupt Input Active When set to a one 1 indicates the Local interrupt input is active Yes No 0 16 Reserved Ye...

Page 48: ... LINTi 15 Local DMA Channel 0 interrupt 21 Table 3 32 PCI Core Features Revision ID PCIHREV BAR0 1 Offset 74 Bits Description Read Write Value after PCI Reset 7 0 PCI Core Features Revision ID This value is read by the RFM 5565 driver to determine the features of this board Yes No Current Rev Table 3 33 DMA Channel 0 Mode Register DMAMODE0 BAR0 1 Offset 80 Bit Description Read Write Value after PC...

Page 49: ...BAR0 1 Offset 84 Bits Description Read Write Value after PCI Reset 31 0 PCI Address Register Indicates from where in PCI Memory space DMA transfers read or write start Yes Yes 0 Table 3 35 DMA Channel 0 Local Address Register DMALADR0 BAR0 1 Offset 88 Bits Description Read Write Value after PCI Reset 31 0 Local Address Register Indicates from where in Local Memory space DMA transfers read or write...

Page 50: ...oundary i e address bits 3 0 are considered to be 0 Yes Yes 0 Table 3 38 DMA Channel 0 Command Status Register DMACSR0 BAR0 1 Offset A8 Bit Description Read Write Value after PCI Reset 0 Channel 0 Enable Writing a one 1 enables channel to transfer data Writing a zero 0 disables the channel from starting a DMA transfer Yes Yes 0 1 Channel 0 Start Writing a one 1 causes channel to start transferring...

Page 51: ...e Specifies which PCI Address bits to use for decoding a PCI access to Local Address Space 1 Each bit corresponds to a PCI Address bit Bit 31 corresponds to address bit 31 Write one 1 to all bits that must be included in decode and zero 0 to all others Used in conjunction with PCIBAR3 Yes No FFE0000 for 2 MB FF00000 for 16 MB FC00000 for 64 MB F800000 for 128 MB F000000 for 256 MB NOTE LAS1RR rang...

Page 52: ...this register A Direct Slave access to an offset from PCIBAR3 maps to the same offset from this Local Base Address Yes Yes 0 NOTE Remap Address value must be a multiple of the LAS1RR range Table 3 41 PCI PIO Direct Slave Local Base Address Remap Continued LAS1BA BAR0 1 Offset F4 Bit Description Read Write Value after PCI Reset Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOUR...

Page 53: ...ite Some bits reserved Some bits read only 17 14 LIER Local Interrupt Enable Reg read write 1B 18 NTD Network Target Data read write 32 Data bits for network target 1C NTN Network Target Node read write Target node ID for network Int 1D NIC Network Interrupt Command read write Select Int type and initiate interrupt 1F 1E Reserved 23 20 ISD1 Int 1 Sender Data read only 127 loc By 32 bit FIFO for ne...

Page 54: ...taining Reflective Memory control and status bits is described below Local Control and Status Register 1 Bit Definitions Bit 31 Status LED The board contains a user defined RED status LED Setting this bit low 0 turns OFF the LED The default state of this bit after reset is high 1 and the LED will be ON Table 3 43 Local Control and Status Register 1 LCSR1 BAR2 Offset 08 Bit 31 Bit 30 Bit 29 Bit 28 ...

Page 55: ...65 SDRAM Note that parity works only on 32 bit and 64 bit accesses Byte 8 bit Word 16 bit and 24 bit memory write accesses are inhibited while parity is enabled Bit 26 Redundant Mode Enabled When this bit is set high 1 redundant mode of network transfers has been enabled This bit is read only Redundant mode is enabled by setting switch S1 position 1 in the ON position Bit 25 Rogue Master 1 Enabled...

Page 56: ...work Offset 1 and Offset 0 will apply an offset to the network address as it is sent or received over the network The offset does not appear on local access to the memory and the offset does not alter network packets as they pass through the board Offset 1 and Offset 0 provide four possible binary increments of 64 MByte each through the 256 MByte network address range When the address and offset e...

Page 57: ...ed RX FIFO Almost Full A logic high 1 indicates the RX FIFO is operating at the maximum acceptable rate Under normal operating conditions this event should not occur This bit is read only within this register To clear this condition write to the corresponding bit within the Local Interrupt Status Register Bit 03 Latched Sync Loss A logic high 1 indicates the receiver circuitry has detected the los...

Page 58: ...rn controlled by Bit 11 of the Local Configuration register INTCSR at offset 68 to Base address 0 The control and status of local interrupts are implemented in the two local registers LISR and LIER The bit functions of these two registers mirror each other Local Interrupt Status Register Local Interrupt Status Register LISR BAR2 Offset 10 This is a 32 bit register containing a group of interrupt s...

Page 59: ...by writing a zero to this bit location Note that Bit 27 of the LCSR1 must be set high before parity is active Also note that parity works only on 32 bit and 64 bit accesses Word 16 bit and byte 8 bit memory write accesses are inhibited Bit 12 Memory Write Inhibited When this bit is high 1 an 8 bit byte a 16 bit word or a 24 bit write to local memory was attempted and inhibited while the board was ...

Page 60: ... FIFO Full When this bit is high 1 the TX FIFO has been full one or more times This bit is latched Once set it must be cleared by writing a zero 0 to this bit location This is a fault condition and data may have been lost NOTE This condition should not occur during normal operation Bit 05 is for diagnostic purposes only Bit 04 Reserved This bit is reserved Bit 03 Reset Node Request When this bit i...

Page 61: ... the target destination node Writing to the NTN register does not initiate the actual network interrupt This register is both read and write accessible The NTN register can be written or read with the Network Interrupt Command Register as a single 16 bit word Table 3 45 Local Interrupt Enable Register LIER BAR2 Offset 14 Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Reserved Bit 23 Bit 2...

Page 62: ...ss pointer for both FIFOs and that pointer is only affected by access to the SID1 FIFO For this reason each location within the data ISD1 FIFO can be read multiple times without incrementing the address pointer while reading the companion SID1 FIFO increments the pointer for both FIFOs For this same reason the user must read the data ISD1 before the Sender ID SID1 or the corresponding data will be...

Page 63: ...k interrupts are pending examine bits 07 02 01 and 00 in the LISR register 3 3 12 Interrupt 2 Sender Data FIFO Interrupt 2 Sender Data FIFO ISD2 BAR2 Offset 28 A 32 bit FIFO functioning just like ISD1 except it responds only to type 2 network interrupts 3 3 13 Interrupt 2 Sender ID FIFO Interrupt 2 Sender ID FIFO SID2 BAR2 Offset 2C An 8 bit FIFO functioning just like SID1 except it responds only ...

Page 64: ...ion No 500 9300875565 000 Rev C 0 Programming 63 Figure 3 1 Block Diagram of the Network Interrupt Reception Circuitry Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 65: ...outine waits for the interrupt to occur 4 After the DMA is finished clear the DMA completion bit with a write to DMACSR0 as follows This is necessary when using DMA interrupts DMA channel 0 Command Status register DMACSR0 at PCIBAR0 offset A8 Write 8 to clear the DMA completion bit before attempting another DMA DMA channel 0 mode setting Bit 9 set to 0 indicates the use of normal Block DMA not Sca...

Page 66: ... block should be aligned on a 16 byte or 8 byte boundary A descriptor chain must be created in PCI 32 bit memory space before starting a Scatter Gather DMA Each descriptor in the chain has this format 1st Dword Lower 32 bit PCI Address for Data each page must be aligned on an 8 byte boundary 2nd Dword Upper 32 bit PCI Address for Data 0 for 32 bit addressing 3rd Dword Number of bytes to transfer t...

Page 67: ...t PCIBAR0 offset A8 Write 8 to clear the DMA completion bit before attempting another DMA DMA channel 0 mode setting Bit 9 set to 1 indicates the use of Scatter Gather DMA not normal Block mode DMAMODE0 at PCIBAR0 offset 80 DMA channel 0 PCI starting address This register is unused during Scatter Gather DMA DMAPADR0 at PCIBAR0 offset 84 DMA channel 0 local starting address Set to the starting addr...

Page 68: ... four window sizes Bits 20 and 21 of RFM register LCSR1 PCIBAR2 Offset 08 indicate the full installed memory size Bit 19 of LCSR1 is connected to S1 switch position 3 and bit 22 of LCSR1 is connected to S1 switch position 4 Both bits 19 and 22 can be read by software 1 when on 0 when off The table below lists the number of PCI PIO window selections available with various RFM 5565 memory options Tw...

Page 69: ...e of installed memory means there are 32 valid base address settings from 00000000 to 03E00000 incrementing by 00200000 all other bits are masked off when written Also a 64 MByte card with a 64 MByte window has no valid base address settings other than the default 0 Since the PCI window size and the Remap register only affect PCI PIO accesses DMA Local to PCI and PCI to Local can be used normally ...

Page 70: ...register at PCIBAR2 offset 10 Determine if the Pending Network Interrupt 4 Bit 07 the Pending Network Interrupt 3 Bit 02 the Pending Network Interrupt 2 Bit 01 or the Pending Network Interrupt 1 Bit 00 is high 1 Assuming for example the previous step indicates Network Interrupt 2 is pending read the Interrupt 2 Sender Data FIFO at PCIBAR2 offset 28 and place the value in the desired user location ...

Page 71: ...ONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED INCLUDING BUT NOT LIMITED TO WARRANTIES OF DESIGN MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ALL OTHER LIABILITY ARISING FROM RELIANCE ON ANY INFORMATION CONTAINED HEREIN IS EXPRESSLY DISCLAIMED Abaco Systems Information Centers Americas 1 866 652 2226 866 OK ABACO or 1 256 880 0444 International Europe Middle East and Africa 44 0 1...

Page 72: ...quipment Have surplus equipment taking up shelf space We ll give it a new home Learn more Visit us at artisantg com for more info on price quotes drivers technical specifications manuals and documentation Artisan Scientific Corporation dba Artisan Technology Group is not an affiliate representative or authorized distributor for any manufacturer listed herein We re here to make your life easier How...

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