Publication No. 500-9300875565-000 Rev. C.0
Programming 43
Table 3-21 PCI Capability Pointer Register
Capability Pointer: Offset $34
Bit
Description
Read Writ
e
Value
after
PCI
Reset
7:0
New Capability Pointer.
Offset into PCI Configuration
Space for the location of the first item in the New
Capabilities Linked List.
Yes
No
$78
31:8
Reserved
Yes
No
$0
Table 3-22 PCI Interrupt Line
PCI Interrupt Line: PCIILR, Offset $3C
Bit
Description
Read Write
*Value
after
PCI
Reset
7:0
Interrupt Line Routing Value.
Value indicates which
input of the system interrupt controller(s) is connected
to each interrupt line of the device.
Yes
Yes
$0
*
NOTE:
This register will be altered by the system BIOS during the system boot process.
Table 3-23 PCI Interrupt Pin
PCI Interrupt Pin: PCIIPR, Offset $3D
Bit
Description
Read Write
Value after
PCI Reset
7:0
Interrupt Pin Register.
Indicates which
interrupt pin the device uses. The following
values are decoded (the Reflective Memory
supports only INTA#).
1 = INTA#
2 = INTB#
3 = INTC#
4 = INTD#
Yes
No
$1
Table 3-24 PCI Min_Gnt
PCI Min_Gnt: PCIMGR, Offset $3E
Bit
Description
Read Write
Value
after PCI
Reset
7:0
Min_Gnt
. Specifies how long a burst period
a device needs, assuming a clock rate of 33
MHz. Value is a multiple of ¼
μ
sec
increments.
Yes
No
$0
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